Sequential Logic Materials taken from: Digital Design and Computer Architecture by David and Sarah Harris & The Essentials of Computer Organization and Architecture by L. Null & J. Lobur

2 3.6 Sequential Circuits Combinational logic circuits are perfect for situations when we require the immediate application of a Boolean function to a set of inputs. There are other times, however, when we need a circuit to change its value with consideration to its current state as well as its inputs. – These circuits have to “remember” their current state. Sequential logic circuits provide this functionality for us.

3 As the name implies, sequential logic circuits require a means by which events can be sequenced. State changes are controlled by clocks. – A “clock” is a special circuit that sends electrical pulses through a circuit. Clocks produce electrical waveforms such as the one shown below. 3.6 Sequential Circuits

4 State changes occur in sequential circuits only when the clock ticks. Circuits can change state on the rising edge, falling edge, or when the clock pulse reaches its highest voltage. 3.6 Sequential Circuits

5 Circuits that change state on the rising edge, or falling edge of the clock pulse are called edge- triggered. Level-triggered circuits change state when the clock voltage reaches its highest or lowest level. 3.6 Sequential Circuits

6 To retain their state values, sequential circuits rely on feedback. Feedback in digital circuits occurs when an output is looped back to the input. A simple example of this concept is shown below. – If Q is 0 it will always be 0, if it is 1, it will always be 1. Why? 3.6 Sequential Circuits

Copyright © 2007 Elsevier 3- A Bistable Feedback Circuit Consider the two possible cases: –Q = 0: then Q = 1 and Q = 0 (consistent) –Q = 1: then Q = 0 and Q = 1 (consistent) Bistable circuit stores 1 bit of state in the state variable, Q (or Q ) But there are no inputs to control the state

Copyright © 2007 Elsevier 3- SR (Set/Reset) Latch SR Latch Consider the four possible cases: –S = 1, R = 0 –S = 0, R = 1 –S = 0, R = 0 –S = 1, R = 1

Copyright © 2007 Elsevier 3- SR Latch Analysis –S = 1, R = 0: then Q = 1 and Q = 0 –S = 0, R = 1: then Q = 0 and Q = 1

Copyright © 2007 Elsevier 3- SR Latch Analysis –S = 1, R = 0: then Q = 1 and Q = 0 –S = 0, R = 1: then Q = 0 and Q = 1

Copyright © 2007 Elsevier 3- SR Latch Analysis –S = 0, R = 0: then Q = Q prev –S = 1, R = 1: then Q = 0 and Q = 0

Copyright © 2007 Elsevier 3- SR Latch Analysis –S = 0, R = 0: then Q = Q prev and Q = Q prev (memory!) –S = 1, R = 1: then Q = 0 and Q = 0 (invalid state: Q ≠ NOT Q)

13 The SR latch actually has three inputs: S, R, and its current output, Q. Thus, we can construct a truth table for this circuit, as shown at the right. Notice the two undefined values. When both S and R are 1, the SR latch is unstable. 3.6 Sequential Circuits

Copyright © 2007 Elsevier 3- D Latch Two inputs: CLK, D –CLK: controls when the output changes –D (the data input): controls what the output changes to Function –When CLK = 1, D passes through to Q (the latch is transparent) –When CLK = 0, Q holds its previous value (the latch is opaque) Avoids invalid case when Q ≠ NOT Q

Copyright © 2007 Elsevier 3- D Latch Internal Circuit

Copyright © 2007 Elsevier 3- D Latch Internal Circuit

Copyright © 2007 Elsevier 3- D Flip-Flop Two inputs: CLK, D Function –The flip-flop “samples” D on the rising edge of CLK When CLK rises from 0 to 1, D passes through to Q Otherwise, Q holds its previous value –Q changes only on the rising edge of CLK A flip-flop is called an edge-triggered device because it is activated on the clock edge

Copyright © 2007 Elsevier 3- D Flip-Flop Internal Circuit Two back-to-back latches (L1 and L2) controlled by complementary clocks When CLK = 0 –L1 is transparent –L2 is opaque –D passes through to N1 When CLK = 1 –L2 is transparent –L1 is opaque –N1 passes through to Q Thus, on the edge of the clock (when CLK rises from 0 1) –D passes through to Q

19 If we can be sure that the inputs to an SR flip-flop will never both be 1, we will never have an unstable circuit. This may not always be the case. The SR flip-flop can be modified to provide a stable state when both inputs are 1. This modified flip-flop is called a JK flip-flop, shown at the right. - The “JK” is in honor of Jack Kilby. 3.6 Sequential Circuits

20 At the right, we see how an SR flip-flop can be modified to create a JK flip-flop. The characteristic table indicates that the flip-flop is stable for all inputs. 3.6 Sequential Circuits

Copyright © 2007 Elsevier 3- Enabled Flip-Flops Inputs: CLK, D, EN –The enable input (EN) controls when new data (D) is stored Function –EN = 1 D passes through to Q on the clock edge –EN = 0 the flip-flop retains its previous state

Copyright © 2007 Elsevier 3- Resettable Flip-Flops Inputs: CLK, D, Reset Function: –Reset = 1 Q is forced to 0 –Reset = 0 the flip-flop behaves like an ordinary D flip-flop

23 This illustration shows a 4-bit register consisting of D flip-flops. You will usually see its block diagram (below) instead. A larger memory configuration is shown on the next slide. 3.6 Sequential Circuits

Sequential Circuits

25 A binary counter is another example of a sequential circuit. The low-order bit is complemented at each clock pulse. Whenever it changes from 0 to 1, the next bit is complemented, and so on through the other flip-flops. 3.6 Sequential Circuits

Copyright © 2007 Elsevier 3- Synchronous Sequential Logic Design Breaks cyclic paths by inserting registers These registers contain the state of the system The state changes at the clock edge, so we say the system is synchronized to the clock Rules of synchronous sequential circuit composition: –Every circuit element is either a register or a combinational circuit –At least one circuit element is a register –All registers receive the same clock signal –Every cyclic path contains at least one register Common synchronous sequential circuits –Finite State Machines (FSMs) –Pipelines –memory

Copyright © 2007 Elsevier 3- Finite State Machine (FSM) Consists of: –State register that Store the current state and Load the next state at the clock edge –Combinational logic that Computes the next state Computes the outputs

28 The behavior of sequential circuits can be expressed using characteristic tables or finite state machines (FSMs). – FSMs consist of a set of nodes that hold the states of the machine and a set of arcs that connect the states. Moore and Mealy machines are two types of FSMs that are equivalent. – They differ only in how they express the outputs of the machine. Moore machines place outputs on each node, while Mealy machines present their outputs on the transitions. 3.6 Sequential Circuits

Copyright © 2007 Elsevier 3- Finite State Machines (FSMs) Next state is determined by the current state and the inputs Two types of finite state machines differ in the output logic: –Moore FSM: outputs depend only on the current state –Mealy FSM: outputs depend on the current state and the inputs

30 The behavior of a JK flop-flop is depicted below by a Moore machine (left) and a Mealy machine (right). 3.6 Sequential Circuits

31 Although the behavior of Moore and Mealy machines is identical, their implementations differ. This is our Moore machine. 3.6 Sequential Circuits

32 Although the behavior of Moore and Mealy machines is identical, their implementations differ. This is our Mealy machine. 3.6 Sequential Circuits

Copyright © 2007 Elsevier 3- Finite State Machine Example Traffic light controller –Traffic sensors: T A, T B (TRUE when there’s traffic) –Lights: L A, L B

Copyright © 2007 Elsevier 3- FSM Black Box Inputs: CLK, Reset, T A, T B Outputs: L A, L B

Copyright © 2007 Elsevier 3- FSM State Transition Diagram Moore FSM: outputs labeled in each state States: Circles Transitions: Arcs

Copyright © 2007 Elsevier 3- FSM State Transition Diagram Moore FSM: outputs labeled in each state States: Circles Transitions: Arcs

Copyright © 2007 Elsevier 3- FSM State Transition Table Current StateInputs Next State STATA TBTB S'S' S00X 1X S1XX S2X0 X1 S3XX

Copyright © 2007 Elsevier 3- FSM State Transition Table Current StateInputs Next State STATA TBTB S'S' S00XS1 S01X S1XXS2 X0S3 S2X1 S3XXS0

Copyright © 2007 Elsevier 3- FSM Encoded State Transition Table Current StateInputsNext State S1S1 S0S0 TATA TBTB S'1S'1 S'0S'0 000X 001X 01XX 10X0 10X1 11XX StateEncoding S000 S101 S210 S311

Copyright © 2007 Elsevier 3- FSM Encoded State Transition Table Current StateInputsNext State S1S1 S0S0 TATA TBTB S'1S'1 S'0S'0 000X01 001X00 01XX10 10X011 10X110 11XX00 StateEncoding S000 S101 S210 S311 S' 1 = S 1  S 0 S' 0 = S 1 S 0 T A + S 1 S 0 T B

Copyright © 2007 Elsevier 3- FSM Output Table Current StateOutputs S1S1 S0S0 LA1LA1 LA0LA0 LB1LB1 LB0LB OutputEncoding green00 yellow01 red10

Copyright © 2007 Elsevier 3- FSM Output Table Current StateOutputs S1S1 S0S0 LA1LA1 LA0LA0 LB1LB1 LB0LB OutputEncoding green00 yellow01 red10 L A1 = S 1 L A0 = S 1 S 0 L B1 = S 1 L B0 = S 1 S 0

Copyright © 2007 Elsevier 3- FSM Schematic: State Register

Copyright © 2007 Elsevier 3- FSM Schematic: Next State Logic

Copyright © 2007 Elsevier 3- FSM Schematic: Output Logic

Copyright © 2007 Elsevier 3- FSM Timing Diagram

Copyright © 2007 Elsevier 3- FSM State Encoding Binary encoding: i.e., for four states, 00, 01, 10, 11 One-hot encoding –One state bit per state –Only one state bit is HIGH at once –I.e., for four states, 0001, 0010, 0100, 1000 –Requires more flip-flops –Often next state and output logic is simpler

Copyright © 2007 Elsevier 3- Moore vs. Mealy FSM Alyssa P. Hacker has a snail that crawls down a paper tape with 1’s and 0’s on it. The snail smiles whenever the last four digits it has crawled over are Design Moore and Mealy FSMs of the snail’s brain.

Copyright © 2007 Elsevier 3- State Transition Diagrams Mealy FSM: arcs indicate input/output

Copyright © 2007 Elsevier 3- Moore FSM State Transition Table Current StateInputsNext State S2S2 S1S1 S0S0 AS'2S'2 S'1S'1 S'0S' StateEncoding S0000 S1001 S2010 S3011 S4100

Copyright © 2007 Elsevier 3- Moore FSM State Transition Table Current StateInputsNext State S2S2 S1S1 S0S0 AS'2S'2 S'1S'1 S'0S' StateEncoding S0000 S1001 S2010 S3011 S4100

Copyright © 2007 Elsevier 3- Moore FSM Output Table Current StateOutput S2S2 S1S1 S0S0 Y

Copyright © 2007 Elsevier 3- Moore FSM Output Table Current StateOutput S2S2 S1S1 S0S0 Y Y = S 2

Copyright © 2007 Elsevier 3- Mealy FSM State Transition and Output Table Current StateInputNext StateOutput S1S1 S0S0 AS'1S'1 S'0S'0 Y StateEncoding S000 S101 S210 S311

Copyright © 2007 Elsevier 3- Mealy FSM State Transition and Output Table Current StateInputNext StateOutput S1S1 S0S0 AS'1S'1 S'0S'0 Y StateEncoding S000 S101 S210 S311

Copyright © 2007 Elsevier 3- Moore FSM Schematic

Copyright © 2007 Elsevier 3- Mealy FSM Schematic

Copyright © 2007 Elsevier 3- Moore and Mealy Timing Diagram

Copyright © 2007 Elsevier 3- FSM Design Procedure Identify the inputs and outputs Sketch a state transition diagram Write a state transition table Select state encodings For a Moore machine: –Rewrite the state transition table with the selected state encodings –Write the output table For a Mealy machine: –Rewrite the combined state transition and output table with the selected state encodings Write Boolean equations for the next state and output logic Sketch the circuit schematic