Gheorghe M. Ştefan

Course: 3 hours/week Text book: Seminar: 2 hours every two weeks Laboratory: 2 hours every two weeks Grading: 30% seminar 40% home works 30% final exam Mandatory: 50% from lab & seminar 2014Digital Integrated Circuits - week one2

WHAT’S A DIGITAL SYSTEM? Framing the digital domain Defining a digital system Our first target 2014Digital Integrated Circuits - week one3

Analog to Digital Conversion (ADC) 2014Digital Integrated Circuits - week one4 s(t): a continuous, analog signal clock : periodic square wave with frequency f clock = 1/T sample rate: samples per second (SPS), is given by 1/T resolution: number of bits used to express the level (3 bits in our example)

2014Digital Integrated Circuits - week one5 Both, sample rate and resolution are doubled Commercial ADC: up to 6 GSPS 6 – 24 bits resolution (at 6 GSPS only 12 bits) 0

Generic digital system 2014Digital Integrated Circuits - week one6

What is computer science? 2014Digital Integrated Circuits - week one7

Digital system. Formal definition 2014Digital Integrated Circuits - week one8 DS = (X, Y, S, f, g) X  {0,1} n is the n-bit input set Y  {0,1} m is the m-bit output set S  {0,1} q is the q-bit internal state (state) set f:(X × S) → S is the state transition function g:(X × S) → Y is the output transition function If x t  X, y t  Y, s t  S s t = f(x t-1, s t-1 ) is a sequential function y t = g(x t, s t ) is a combinational function

Digital Circuit: the simplest embodiment of a Digital System Binary configurations: input: X n-1, X n-2, … X 0 output: Y m-1, Y m-2, … Y 0 state: S q-1, S q-2, … S 0 with: X i, Y j, S k,  {0,1} coded with: 0 Volt for Volt for 1 combinational circuits registers clock signal 2014Digital Integrated Circuits - week one9

Combinational circuit 2014Digital Integrated Circuits - week one10 On in all n-bit binary configurations must be considered Output can change at any input bit switch : On out some (rarely all) of m-bit binary configurations are considered t p : propagation time shaded time interval: transition time from F(in1) to F(in2)

The Register 2014Digital Integrated Circuits - week one11 t su : set-up time t hold : hold time t p : propagation time from active edge of clock to output T clock : the period of the clock signal … t i-1 t i t i+1 … : discrete ticking time shaded interval: the input can change in this time interval

Digital system in Verilog HDL 2014Digital Integrated Circuits - week one12

2014Digital Integrated Circuits - week one13 The content of file 0_parameter.v : Color code: blue – reserved words green – comments orange - numbers

The result of synthesis 2014Digital Integrated Circuits - week one14 stateTransition combinational module is instantiated as s tateTrans outputTransition combinational module is instantiated as outTrans fd is the register; its output goes forward to outTrans and backward to close the loop though stateTrans module

Our first target 2014Digital Integrated Circuits - week one15 Rare and isolated wrong pixels must be corrected. No video sensor is perfect. s(t) : the input sample at the moment t s’(t) : the corrected sample at the moment t The algorithm: s’(t) = if (s(t)= 0) then (s(t-1) + s(t+1))/2 else s(t)

The error 2014Digital Integrated Circuits - week one16

The actual timing 2014Digital Integrated Circuits - week one17

To make the correction, three successive values: in (t-3] in (t-2) in(t-1) must be loaded as the internal state of the circuit. The structure of the internal state consists of 3 sub-states: State[11:0] = {ss3[3:0],ss2[3:0],ss1[3:0]} State transition function: state(t) = {ss3, ss2, ss1} state(t+1) = {ss2, ss1, in(t)} Output transition function: Out(t) = (ss2 = 0) ? (ss3+ss1)/2 : ss2 Results a latency of 2 clock cycles 2014Digital Integrated Circuits - week one18

2014 Digital Integrated Circuits - week one19 state[11:8] = xxxx state[7:4] = xxxx state[3:0] = xxxx + /2 sel = 0 ? in = xxxx xxxx out = xxxx x clock 01

2014 Digital Integrated Circuits - week one20 state[11:8] = xxxx state[7:4] = xxxx state[3:0] = xxxx + /2 sel = 0 ? in = 0111 xxxx out = xxxx x clock 01

2014 Digital Integrated Circuits - week one21 state[11:8] = xxxx state[7:4] = xxxx state[3:0] = /2 sel = 0 ? in = 1001 xxxx out = xxxx 0 clock 01

2014 Digital Integrated Circuits - week one22 state[11:8] = xxxx state[7:4] = 0111 state[3:0] = /2 sel = 0 ? in = 1010 xxxx out = clock 01

2014 Digital Integrated Circuits - week one23 state[11:8] = 0111 state[7:4] = 1001 state[3:0] = /2 sel = 0 ? in = out = clock 01

2014 Digital Integrated Circuits - week one24 state[11:8] = 1001 state[7:4] = 1010 state[3:0] = /2 sel = 0 ? in = out = clock 01

2014 Digital Integrated Circuits - week one25 state[11:8] = 1010 state[7:4] = 1011 state[3:0] = /2 sel = 0 ? in = out = clock 01

2014 Digital Integrated Circuits - week one26 state[11:8] = 1011 state[7:4] = 1100 state[3:0] = /2 sel = 0 ? in = out = clock 01

2014 Digital Integrated Circuits - week one27 state[11:8] = 1100 state[7:4] = 1011 state[3:0] = /2 sel = 0 ? in = out = clock 01

2014 Digital Integrated Circuits - week one28 state[11:8] = 1011 state[7:4] = 1010 state[3:0] = /2 sel = 0 ? in = out = clock 01

2014 Digital Integrated Circuits - week one29 state[11:8] = 1010 state[7:4] = 1000 state[3:0] = /2 sel = 0 ? in = out = clock 01

2014 Digital Integrated Circuits - week one30 state[11:8] = 1000 state[7:4] = 0101 state[3:0] = /2 sel = 0 ? in = out = clock 01

2014 Digital Integrated Circuits - week one31 state[11:8] = 0101 state[7:4] = 0011 state[3:0] = /2 sel = 0 ? in = out = clock 01

2014 Digital Integrated Circuits - week one32 state[11:8] = 0011 state[7:4] = 0010 state[3:0] = /2 sel = 0 ? in = out = clock 01

2014 Digital Integrated Circuits - week one33 state[11:8] = 0010 state[7:4] = 0010 state[3:0] = /2 sel = 0 ? in = out = clock 01

2014 Digital Integrated Circuits - week one34 state[11:8] = 0010 state[7:4] = 0000 state[3:0] = /2 sel = 0 ? in = out = clock 01

2014 Digital Integrated Circuits - week one35 state[11:8] = 0000 state[7:4] = 0101 state[3:0] = /2 sel = 0 ? in = out = clock 01

2014Digital Integrated Circuits - week one36

2014Digital Integrated Circuits - week one37

Simulation 2014Digital Integrated Circuits - week one38

Simulation (cont) 2014Digital Integrated Circuits - week one39

Synthesis: top level 2014Digital Integrated Circuits - week one40

Synthesis: second level 2014Digital Integrated Circuits - week one41

Synthesis: third level 2014Digital Integrated Circuits - week one42

The functions involved in digital pixel correction The predicate function - (ss2 = 0) - used to detect the wrong pixel The addition function, used to compute the interpolation The division by 2 function, used to compute the interpolation The selection function, according to the result of the predicate function select the result of interpolation or the current value The storage function, triggered by the active edge of clock, used to store the internal state of the system 2014Digital Integrated Circuits - week one43

The first crossing through the matter Main targets: Form behavioral to structural description in Verilog Working with simple combinational functions Learning about the internal structure of register Simple applications Provide the motivation for: Understand the transistor level description of a logic circuit Designing digital systems using digital circuits 2014Digital Integrated Circuits - week one44

DIGITAL CIRCUITS Combinational circuits Zero circuit Selection circuit (multiplexor) Adder Divider Sequential circuits Elementary latches Clocked latches (transparent on the active level) Master-Slave flip-flops (triggered by the active edge) Register Applications Shift register Counter 2014Digital Integrated Circuits - week one45

Combinational circuits 2014Digital Integrated Circuits - week one46 xyxy(xy)’ xy xyxy(x  y)’ xyx+y(x+y)’

Zero circuit: a n-input NOR 2014Digital Integrated Circuits - week one47 fan-in: number of inputs of a logic circuit depth: number of logic levels of a logic circuit size: the total number of inputs in all the circuits fan-in = 2 depth = 1 size = 2 fan-in = n depth = 1 size = n fan-in = 8 depth = 7 size = 14 fan-in = 8 depth = 3 size = 14

Selection circuit (multiplexer) 2014Digital Integrated Circuits - week one48 out = sel in1 + sel’ in0

2014Digital Integrated Circuits - week one49 Behavioral: Structural:

Synthesis result for n = Digital Integrated Circuits - week one50

Adder 2014Digital Integrated Circuits - week one51 For n=1, results the one-bit adder. The logic expressions are sum = a  b  c = (a  b)  c carry = a b + c (a  b)

2014Digital Integrated Circuits - week one52 sum = a’b’c + a’bc’ + ab’c’ + abc = a’(b’c + bc’) + a(b’c’ + bc) = a’(b  c) + a(b  c)’ = a  (b  c) = a  b  c carry = a’bc + ab’c + abc’ + abc= = (a’b+ab’)c+ab(c’+c)= = (a  b)c + ab

Integer divide by 2 == right shift Integers Positive integers: from 8’b0000_0000 = 0 to 8’b1111_1111 = +255 Signed integers: from 8’b1_ = -128 through 8’b0_ = 0 to 8’b0_ = +127 Negative integer is the positive one, complemented =0_ >1_ =1_ =-127 Divide by 2 For positive integers: logic right shift (with 0 input) 8’b1001_1100 (156) => 8’b0100_1110 (78) For signed integers: arithmetic right shift (with sign input) - sign is preserved 8’b1_ (-70) => 8’b1_ (-35) 2014Digital Integrated Circuits - week one53

Home work 1 Problems from 2.1 to 2.7; see Text Book at Send your home work as a one-file word document to With the subject: CID_42x_LastName_FirstName_TCy Example: CID_421_Popescu_Ion_TC4 2014Digital Integrated Circuits - week one54