SoC Verification HW #2 TA: Wei-Ting Tu Assignment: 04/12/06 Due: 04/26/06

Lab introductions Lab 1-3: examples Lab 4-6: exercises Lab requirements Implement each task in lab 4~6. References svtb.pdf: SystemVerilog TestBench Guide svtb_tutorial.pdf: SystemVerilog TestBench Tutorial SVTB_2005.06_SG.pdf: SystemVerilog Workshop Student Guide SVTB_2005.06_LG_01~3.pdf: SystemVerilog Workshop examples SVTB_2005.06_LG_04~6.pdf: SystemVerilog Workshop exercises

Workshop Goal Acquire the skills to write a SystemVerilog testbench to verify Verilog/SystemVerilog RTL code with coverage-driven random stimulus.

Target Audience Design or Verification engineers writing SystemVerilog testbenches to verify Verilog or SystemVerilog code.

Workshop Prerequisites You must have experience in the following areas: Familiarity with a UNIX text editor Basic programming skills in Verilog, VHDL or C Debugging experience with Verilog, VHDL or C

What Is the Device Under Test? A router: 16 x 16 crosspoint switch din [15:0] dout [15:0] frame_n[15:0] frameo_n [15:0] router valid_n [15:0] valido_n [15:0] reset_n The router has 16 input and 16 output ports. Each input and output port consists of 3 signals, serial data, frame and valid. These signals are represented in a bit-vector format, din[15:0], frame_n[15:0], valid_n[15:0], dout[15:0], frameo_n[15:0] and valido_n[15:0]. To drive an individual port, the specific bit position corresponding to the port number must be specified. For example, if input port 3 is to be driven, then the corresponding signals shall be din[3], frame_n[3] and valid_n[3]. To sample an individual port, the specific bit position corresponding to the port number must be specified. For example, if output port 7 is to be sampled, then the corresponding signals shall be dout[7], frameo_n[7] and valido_n[7]. clock

A Functional Perspective inputs outputs port port frame_n[0] frameo_n[0] valid_n[0] valido_n[0] din[0] dout[0] 1 1 2 2 3 3 4 4 partial view

The Router Description Single positive-edge clock Input and output data are serial (1 bit / clock) Packets are sent through in variable length: Each packet is composed of two parts Header Payload Packets can be routed from any input port to any output port on a packet-by-packet basis No internal buffering or broadcasting (1-to-N)

Input Packet Structure frame_n: Falling edge indicates first bit of packet Rising edge indicates last bit of packet din: Header (destination address & padding bits) and payload valid_n: valid_n is low if payload bit is valid, high otherwise clock din[i] x A0 A1 A2 A3 d0 .... x dn-1 dn x valid_n[i] x x x x x frame_n[i] dest. address pad payload

Output Packet Structure Output activity is indicated by: frameo_n, valido_n, and dout Data is valid only when: frameo_n output is low (except for last bit) valido_n output is low Header field is stripped clock dout[i] x x d0 d1 x x d2 d3 dn-3 x dn-2 dn-1 x valido_n[i] x x frameo_n[i]

Reset Signal While asserting reset_n, frame_n and valid_n must be de-asserted reset_n is asserted for at least one clock cycle After de-asserting reset_n, wait for 15 clocks before sending a packet through the router clock reset_n frame_n[i] 15 clock cycles During these 15 clock cycles, the router is performing self-initialization. If you attempt to drive a packet through the router during this time, the self-initialization will fail and the router will not work correctly afterwards.

The DUT: router.v The Design Under Test, router.v, is a Verilog file: Located under the rtl directory From the lab workspace: ../../rtl/router.v ~ labs/ solutions/ rtl/ lab1/ lab6/ lab1/ lab2/ lab6/ router.v lab work files

The SystemVerilog Test Environment Monitor Transactor Self Check Observes data from DUT Identifies transactions Checks correctness Coverage Driver Generator DUT Configure completeness Test program Top level harness file interface

SystemVerilog Testbench Building Process simv router.vr.tmp ntb_template -t router router.v router.if.vrh router.test_top.sv Discard vcs –sverilog router.test_top.sv router.tb.sv router.if.sv router.v router.if.sv router.tb.sv Top level harness Interface Test program router.test_top.v router.v

Create Verilog Test Harness File Use VCS template generator Generates three files: router.test_top.v Verilog test harness file router.if.vrh Discard (for OpenVera only) router.vr.tmp Discard (for OpenVera only) -t router Specifies DUT module name router.v DUT source code file router.test_top.v will be used to help build SystemVerilog testbench files ntb_template -t router router.v router.v must be the last entry in the ntb_template command.

Creating SystemVerilog Interface File Create interface file from router.test_top.v Encapsulate signals in interface block cp router.test_top.v router.if.sv module router_test_top; parameter simulation_cycle = 100; reg SystemClock ; wire reset_n ; wire [15:0] din ; wire clock ; wire [15:0] frame_n ; wire [15:0] valid_n ; wire [15:0] dout ; wire [15:0] busy_n ; wire [15:0] valido_n ; wire [15:0] frameo_n ; `ifdef SYNOPSYS_NTB ... `endif router dut( … ); initial begin SystemClock = 0 ; forever begin #(simulation_cycle/2) SystemClock = ~SystemClock ; end endmodule Create from default harness file Change module to interface Delete all except wires interface router_io(input logic clock); logic reset_n ; logic [15:0] din ; //wire clock; logic [15:0] frame_n ; logic [15:0] valid_n ; logic [15:0] dout ; logic [15:0] busy_n ; logic [15:0] valido_n ; logic [15:0] frameo_n ; endinterface Move clock to input argument router.if.sv router.test_top.v Change wire to logic

Define Test Program Interface Port By default all interface signals are asynchronous Synchronous signals can be created via clocking block and connected to test program via modport router.if.sv interface router_io(input logic clock); logic reset_n ; logic [15:0] din ; logic [15:0] frame_n ; logic [15:0] valid_n ; logic [15:0] dout ; logic [15:0] busy_n ; logic [15:0] valido_n ; logic [15:0] frameo_n ; clocking cb @(posedge clock); default input #1 output #1; output reset_n; output din; output frame_n; output valid_n; input dout; input busy_n; input valido_n; input frameo_n; endclocking modport TB(clocking cb, output reset_n); endinterface Monitor Transactor Self Check Coverage Driver Generator DUT Configure Create synchronous by placing signals into clocking block If unspecified, the sample and drive skew defaults to: default input #1 output #0; Sample/drive skew Define connection for test program with modport Direction w/respect to test Synchronous Asynchronous

Both synchronous and asynchronous signals are encapsulated in modport Build Testbench Testbench is encapsulated in program block List interface signals in argument Both synchronous and asynchronous signals are encapsulated in modport router.tb.sv program automatic router_test(router_io.TB router); // develop test code in initial block: initial begin $vcdpluson; // Dumping file control $display(“Hello World”); end endprogram Monitor Transactor Self Check Coverage Driver Generator DUT Configure

Sample Testbench Develop test program code in initial block program automatic router_test(router_io.TB router); //testbench code in initial block: initial begin $vcdpluson; // Dumping file control // $display(“Hello World”); end reset(); task reset(); router.reset_n <= 1’b0; router.cb.frame_n <= 16’hffff; router.cb.valid_n <= ~(’b0); ##2 router.cb.reset_n <= 1’b1; // reset_n can be both synchronous and asynchronous repeat(15) @(router.cb); endtask endprogram interface router_io(input logic clock); logic reset_n ; logic [15:0] din ; logic [15:0] frame_n ; logic [15:0] valid_n ; ... clocking cb @(posedge clock); default input #1 output #1; output reset_n; output din; output frame_n; output valid_n; endclocking modport TB(clocking cb, output reset_n); endinterface Asynchronous signals are driven without reference to clocking block Synchronous signals are driven via clocking block Advance clock cycles via clocking block

Driving Synchronous Device Signals [##num] interface.cb.signal <= <value> or <variable expression>; Must be driven with <= (non-blocking assignment) Can be specified with ##num of clocks delay Equivalent to: repeat(num) @(router.cb); router.din[3] <= #input_skew_value var_a; router.cb.din[3] = 1’b1; // error (must be non-blocking) ##1 router.cb.din[3] <= var_a; clock var_a din[3] Statement executes here Variable expression evaluates Apply drive here Next statement executes

Sampling Synchronous Device Signals variable = interface.cb.signal; No delay attribute (## num) Variable is assigned the sampled value Sampling of output signal is not allowed Examples: data[i] = router.cb.dout[7]; all_data = router.cb.dout; @(posedge router.cb.frameo_n[7]); $display(“router.cb.din = %b\n”, router.din); //error if(router.cb.din[3] == 1’b0) //error

Advancing Simulation Time Asynchronous (Verilog coding style): #delay; @(negedge interface.signal); Synchronous (advancing clock cycles): Verilog coding style: @(posedge interface.clock_signal); repeat (10) @(posedge interface.clock_signal); SystemVerilog coding style (clocking block): @(interface.clocking_block); repeat (10) @(interface.clocking_block); Each clocking block specifies a clock signal and edge: In order for the syntax @(posedge interface.clock_signal); to work. The clock_signal must be passed in as an additional asynchronous signal argument to the modport for the test program connection: interface router_io(input logic clock); logic reset_n ; logic [15:0] din ; logic [15:0] frame_n ; logic [15:0] valid_n ; logic [15:0] dout ; logic [15:0] busy_n ; logic [15:0] valido_n ; logic [15:0] frameo_n ; clocking cb @(posedge clock); default input #1 output #1; output reset_n; output din; output frame_n; output valid_n; input dout; input busy_n; input valido_n; input frameo_n; endclocking modport TB(clocking cb, output reset_n, input clock); endinterface interface router_io(input logic clock); clocking cb @(posedge clock); ... endclocking endinterface

Create SystemVerilog Harness File Create harness file from router.test_top.v mv router.test_top.v router.test_top.sv Monitor Transactor Self Check Coverage Driver Generator DUT Configure module router_test_top; parameter simulation_cycle = 100; reg SystemClock ; wire reset_n ; wire clock ; wire [15:0] frame_n ; wire [15:0] valid_n ; wire [15:0] din ; wire [15:0] dout ; wire [15:0] busy_n ; wire [15:0] valido_n ; wire [15:0] frameo_n ; `ifdef SYNOPSYS_NTB ... `endif router dut( … ); initial begin SystemClock = 0 ; forever begin #(simulation_cycle/2) SystemClock = ~SystemClock ; end endmodule Delete all wire declarations and all OpenVera stuff module router_test_top; parameter simulation_cycle = 100; reg SystemClock ; router dut( … ); initial begin SystemClock = 0 ; forever begin #(simulation_cycle/2) SystemClock = ~SystemClock ; end endmodule router.test_top.sv router.test_top.sv

Complete Top Level Harness File Instantiate test program and interface in harness file Instantiate interface Connect SystemClock to interface block router.test_top.sv module router_test_top; parameter simulation_cycle = 100; reg SystemClock ; router dut( .reset_n(reset_n), .clock(clock), .frame_n(frame_n), .valid_n(valid_n), .din(din), .dout(dout), .busy_n(busy_n), .valido_n(valido_n), .frameo_n(frameo_n)); initial begin SystemClock = 0 ; forever begin #(simulation_cycle/2) SystemClock = ~SystemClock ; end endmodule module router_test_top; parameter simulation_cycle = 100; reg SystemClock; router_io top_io(SystemClock); router_test test(top_io); router dut(.reset_n(top_io.reset_n), .clock(top_io.clock), .frame_n(top_io.frame_n), .valid_n(top_io.valid_n), .din(top_io.din), .dout(top_io.dout), .busy_n(top_io.busy_n), .valido_n(top_io.valido_n), .frameo_n(top_io.frameo_n)); initial begin SystemClock = 0 ; forever begin #(simulation_cycle/2) SystemClock = ~SystemClock ; end endmodule Instantiate test program Update DUT instantiation using interface connection If the DUT module was already constructed with SystemVerilog interface, the connection would simplify to: router dut(top_io);

Compile RTL & Simulate w/ VCS NTB Monitor Transactor Self Check Coverage Driver Generator DUT Configure router.tb.sv router.test_top.sv router.if.sv router.v Compile HDL code: (generate simv simulation binary) > vcs –sverilog [-debug] router.test_top.sv \ router.tb.sv router.if.sv router.v Get vcs compiler switch summary: > vcs -help Simulate DUT with SystemVerilog testbench: (running simv) > ./simv