By: Aidahani Binti Ahmad

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Presentation transcript:

By: Aidahani Binti Ahmad SMP CACHE 2.0 SIMULATOR Project 5 : Influence of the Mapping for Different Cache Sizes. By: Aidahani Binti Ahmad [ M031010031 ]

Design parameters of caches Capacity – total number of blocks the cache can hold. Block size – the number of bytes that are loaded from and written to memory at a time. Associativity – in an N-way set associative cache, a particular block can be loaded in N different cache locations. Replacement policy – which block do we remove from the cache as a new block is loaded. In modern machines, more than one cache is placed between the main memory and the processor.

Project configuration: Configure a system with the following architectural characteristics: • Processors in SMP = 1. • Cache coherence protocol = MESI. • Scheme for bus arbitration = Random. • Word wide (bits) = 32. • Words by block = 64 (block size = 256 bytes). • Blocks in main memory = 4096 (main memory size = 1024 KB). • Replacement policy = LRU. Configure the mapping using : Direct Two-way set associative Four-way set associative Eight-way set associative Fully-associative (remeber: Number_of_ways = Number_of_blocks_in_cache / Number_of_cache_sets).

Project configuration: For each of the configurations of mapping, configure the number of blocks in cache in order to get the following cache sizes: 4 KB (16 blocks in cache) 8 KB (32 blocks in cache) 16 KB (64 blocks in cache) 32 K (128 blocks in cache). For each configuration obtain the miss rate using the memory trace: Ear.

Purpose: Analyze the influence f the mapping on the miss rate for several cache sizes. Simulator Finding: Mapping Cache Size (kb) 4KB 8KB 16KB 32KB 16 block 32 block 64 block 128 block Direct 12.34 7.0271 5.9344 4.0317 2-Way Associative 8.3082 6.7822 3.8809 2.8636 4-Way Associative 6.6315 4.8229 2.939 2.468 8-way Associative 6.5938 5.2562 2.694 2.3361 Full Associative 6.5373 5.1243 2.3962

Does the miss rate increase or decrease as the associativity increases Does the miss rate increase or decrease as the associativity increases? Why? Figure 1: The Miss Rate against mapping type and cache size

Base on the analysis of the finding in Figure 1 it shown that the degree of misses rate decreases when increasing the associative. This because its will be more flexible placement and the conflict misses are reduced. However, 8-way set associative cache has almost the same miss rate as fully associative cache. The most flexible cache system is the fully associative cache where in a fully associative cache subsystem, the caching controller can place a block of bytes in any one of the cache lines present in the cache memory. Greater associativity can come at the great cost.

What does it happen with the conflict misses when you enlarge the associativity grade? Conflict misses means if we use direct-mapped or set-associative strategy two blocks may map to the same record in cache. Figure 2: Miss Rate of associative compare with cache size.

Conflict misses decrease significantly with increased associativity, especially for smaller caches. Finally, note in Figure 2 that between 16KB there is a large difference of miss rate between direct-mapped and fully associative caches. This difference is the conflict miss rate. The insight from looking at conflict miss rates is that secondary caches benefit a great deal from high associativity.

Does the influence of the associativity grade increase or decrease as the cache size increases? Why?

The associative ways influence decreases with larger caches because the benefits are every time less significant. This conclusion coincides with the theory that conflict misses are reduced by increasing the associativity, however, in large caches this kind of misses are less frequent this can be view in figure 3 where the incluence of associative is very much similar between 8-way associative and full associative.

In conclusion, does the increase of associativity improve the system performance? If the answer is yes, in general, which is the step with more benefits: from direct to 2-way, from 2- way to 4-way, from 4-way to 8-way, or from 8-way to fully-associative?

The system efficiency does improve with increasing the associative ways but the maximum efficiency improvement is – [i] from direct to set- associative with 2 rows in set (2-way). Cache Rule: the miss rate of a direct-mapped cache of size N is about the same as a two way set-associative cache of size N/2. An 8-way set-associative cache has about the same miss rate as a fully associative cache. A two-way set associative cache is much better than a direct-mapped cache and considerably less complex than a fully associative cache. However, if you're still getting too many conflicts, you might consider using a four-way set associative cache.

Thank You