John Dusatko 2012 EPICS Timing Workshop The SLAC Timing System April 24, The Accelerator Timing System at SLAC: Experiences, Ideas & Future Plans 2012 EPICS Timing Workshop John Dusatko SLAC I&C Division / EE Department
John Dusatko 2012 EPICS Timing Workshop The SLAC Timing System April 24, Introduction ►This talk will focus on the SLAC Timing System giving a bit of history up to the development of the LCLS-I timing system and relate some of our experiences from that. ►This is followed by a description of our plans for LCLS-II and other systems ► Finally, I’ll present some ideas/wishlist for new features
John Dusatko 2012 EPICS Timing Workshop The SLAC Timing System April 24, Background / History Legacy Timing System: Developed in the 1980s for the SLC: CAMAC-based, generates triggers based on six AC mains-derived “Timeslot” signals Whole system triggered off of 360Hz “Fiducial” (Generated from the three AC mains phases) Uses obsolete components *Still* in use (ran part of LCLS-I before upgrade and still running FACET) LCLS-I: Gave us the chance to develop a new timing system: Decision to use MRF Event System Had to co-exist with original SLC timing and was initially slaved to it (no longer following upgrade) This requirement affected some of our design decisions
John Dusatko 2012 EPICS Timing Workshop The SLAC Timing System April 24, DEVDEV LCLS-I Timing/Event System Architecture ~ Linac main drive line Sync/Div SLC MPG PNETPNET 119 MHz 360 Hz SLC events LCLS events PNETPNET PP PDUPDU EVREVR OCOC TTL-NIM convert. Digitizer LLRF BPMs Toroids Cameras Wire Scanner SLC klystrons TTL SLC Trigs FANFAN OCOC Low Level RF EPICS Network fiber distribution LCLS Timing System components are in RED EVGEVG LCLS Master Oscillator 476 MHz Linac Master Osc LCLS-I Timing as originally implemented / Slaved to SLC Timing: formed event codes from SLC Timing Pattern (PNET) FIDOPDU Raw 360 Hz LCLS Timeslot Trigger TRD Tx TRD Rx 119Mhz + FID Sq Wave on Coax119Mhz + FID Sq Wave on Coax Fiber Cable TO: - Cav BPM - MPS BLM - MPS PIC - BCS TRD Rx Master Pattern Generator
John Dusatko 2012 EPICS Timing Workshop The SLAC Timing System April 24, LCLS-I Timing/Event System Architecture DEVDEV ~ Linac main drive line Sync/Div VMTGVMTG 119 MHz 360 Hz IRQ & Timeslot LCLS events EVREVR CPUCPU TTL-NIM convert. TTL FANFAN CPUCPU EPICS Network Fiber distribution EVGEVG LCLS Master Oscillator 476 MHz Linac Master Osc FIDOPDU Raw 360 Hz LCLS Timeslot Trigger TRD Tx TRD Rx 119Mhz + FID Sq Wave on Coax 119Mhz + FID Sq Wave on Coax Fiber Cable TO: - Cav BPM - MPS BLM - MPS PIC - BCS 60Hz Timeslot 1 From MPS (Enet) LCLS-I Timing De-Coupled from the SLC System. VMTG module provides Timeslot info and CPU forms event codes directly. The LCLS-II Timing System will look very similar to this Digitizer LLRF BPMs Toroids Cameras Wire Scanner SLC klystrons
John Dusatko 2012 EPICS Timing Workshop The SLAC Timing System April 24, LCLS-I Timing System Features & Comments: Has ~122 EVRs across 1.5KM of machine (not counting dev units) 85 PMC EVRs 37 VME EVRs (LLRF & BPM Subsystems) Due to distances, we had to use Single-Mode Fiber (replaced Multi-Mode SPFs with SM) Developed Separate TRD (Timing Reference Distribution) subsystem to provide 119MHZ w/360Hz phase-modulated fiducial to systems that didn’t need overhead of an EVR Developed Custom HW (Sync/Div, TRD, VMTG) in addition to MRF Event HW Extensive SW development effort (more so than the HW dev) Made some changes to MRF HW
John Dusatko 2012 EPICS Timing Workshop The SLAC Timing System April 24, LCLS-II Timing System LCLS-II will timing will be very similar to LCLS-I Have its own EVG LCLS-II will run on different timeslots than LCLS-I Both LCLS-I & -II timing systems will “know” about each other (via a synchronizing signal) Using uTCA platform as well as VME
John Dusatko 2012 EPICS Timing Workshop The SLAC Timing System April 24, LCLS-II Timing System Micro TCA Will be used in at least the BPM subsystem, possibly LLRF as well Development effort underway Interim timing solution: PMC-EVR-200 on uTCA adapter Planning on using/adapting Stockholm University uTCA Timing Module (dev’d for XFEL) as final solution - Developed for XFEL - Distributes triggers & clock on uTCA backplane - Double-wide (with RTM I/O) in development - Contains fiber phase stabilization mechanism
John Dusatko 2012 EPICS Timing Workshop The SLAC Timing System April 24, Other SLAC Machines & Future Plans FACET: (1 st 2/3 rd of Linac) Uses SLC timing for all Legacy Systems Uses Event System for all new subsystems (accelerator controls as well as experiments) XTA: X-Band Test Accelerator (stand-alone machine) Uses Event System for timing / coupled to SLC timing SPEAR-III: Considering Event System for booster upgrade PEP-X: Could/Would use Event System in some form Grand SLAC Timing System: Would tie together all related systems (don’t know what this would look like yet…)
John Dusatko 2012 EPICS Timing Workshop The SLAC Timing System April 24, Timing Features Wishlist Desired Features: EVR Standby trigger capability FPGA Gateware mod to EVR to support stby triggers (completed on VME-EVR) Greater than 256 event codes Experiment support keeps asking for more ECs! Fanout Module Upgrade Added diagnostics for SFP status readout & single-level fanout ports Fiber Phase Stabilization SU uTCA module has this feature Additional Diagnostics on EVG side Readout of parameters (RF power, phase, fiducial rate, etc.) from Sync/Div chassis EVR SFP (optical xcvr) Diagnostics Readout for maintenance