CSIE30300 Computer Architecture Unit 15: Multiprocessors Hsin-Chou Chi [Adapted from material by and

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Presentation transcript:

CSIE30300 Computer Architecture Unit 15: Multiprocessors Hsin-Chou Chi [Adapted from material by and

Parallel Computers Definition: “A parallel computer is a collection of processiong elements that cooperate and communicate to solve large problems fast.” Questions about parallel computers: –How large a collection? –How powerful are processing elements? –How do they cooperate and communicate? –How are data transmitted? –What type of interconnection? –What are HW and SW primitives for programmer? –Does it translate into performance?

Why Multiprocessors? 1.Microprocessors as the fastest CPUs Collecting several much easier than redesigning 1 2.Complexity of current microprocessors Do we have enough ideas to sustain 1.5X/yr? Can we deliver such complexity on schedule? 3.Slow (but steady) improvement in parallel software (scientific apps, databases, OS)

Communication Models Shared Memory –Processors communicate with shared address space –Easy on small-scale machines –Advantages: »Model of choice for uniprocessors, small-scale MPs »Ease of programming »Lower latency »Easier to use hardware controlled caching Message passing –Processors have private memories, communicate via messages –Advantages: »Less hardware, easier to design »Focuses attention on costly non-local operations Can support either SW model on either HW base

Small-Scale—Shared Memory Caches serve to: –Increase bandwidth versus bus/memory –Reduce latency of access –Valuable for both private data and shared data What about cache consistency?

An Example Snoopy Protocol Invalidation protocol, write-back cache Each block of memory is in one state: –Clean in all caches and up-to-date in memory (Shared) –OR Dirty in exactly one cache (Exclusive) –OR Not in any caches Each cache block is in one state (track these): –Shared : block can be read –OR Exclusive : cache has only copy, its writeable, and dirty –OR Invalid : block contains no data Read misses: cause all caches to snoop bus Writes to clean line are treated as misses