EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 1 Digital Integrated Circuits A Design Perspective Arithmetic Circuits Reference: Digital Integrated Circuits, 2nd edition, Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic Disclaimer: slides adapted for INE5442/EEL7312 by José L. Güntzel from the book´s companion slides made available by the authors.

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 2 A Generic Digital Processor

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 3 Building Blocks for Digital Architectures Arithmetic unit - Bit-sliced datapath(adder, multiplier, shifter, comparator, etc.) Memory - RAM, ROM, Buffers, Shift registers Control - Finite state machine (PLA, random logic.) - Counters Interconnect - Switches - Arbiters - Bus

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 4 An Intel Microprocessor Itanium has 6 integer execution units like this

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 5 Bit-Sliced Design

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 6 Bit-Sliced Datapath

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 7 Itanium Integer Datapath Fetzer, Orton, ISSCC’02

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 8 Adders

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 9 Full-Adder

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 10 The Binary Adder

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 11 Express Sum and Carry as a function of P, G, D Define 3 new variable which ONLY depend on A, B Generate (G) = AB Propagate (P) = A  B Delete =A B Can also derive expressions for S and C o based on D and P Propagate (P) = A  B Note that we will be sometimes using an alternate definition for

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 12 The Ripple-Carry Adder Worst case delay linear with the number of bits Goal: Make the fastest possible carry path circuit t d = O(N) t adder = (N-1)t carry + t sum

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 13 Complimentary Static CMOS Full Adder 28 Transistors

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 14 Inversion Property

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 15 Minimize Critical Path by Reducing Inverting Stages Exploit Inversion Property

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 16 A Better Structure: The Mirror Adder

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 17 Mirror Adder Stick Diagram

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 18 The Mirror Adder The NMOS and PMOS chains are completely symmetrical. A maximum of two series transistors can be observed in the carry- generation circuitry. When laying out the cell, the most critical issue is the minimization of the capacitance at node C o. The reduction of the diffusion capacitances is particularly important. The capacitance at node C o is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell. The transistors connected to C i are placed closest to the output. Only the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size.

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 19 Transmission Gate Full Adder

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 20 Manchester Carry Chain

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 21 Manchester Carry Chain

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 22 Manchester Carry Chain Stick Diagram

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 23 Carry-Bypass Adder Also called Carry-Skip

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 24 Carry-Bypass Adder (cont.) t adder = t setup + M tcarry + (N/M-1)t bypass + (M-1)t carry + t sum

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 25 Multipliers

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 26 The Binary Multiplication

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 27 The Binary Multiplication

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 28 The Array Multiplier

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 29 The MxN Array Multiplier — Critical Path Critical Path 1 & 2

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 30 Carry-Save Multiplier

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 31 Multiplier Floorplan

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 32 Shifters

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 33 The Binary Shifter

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 34 The Barrel Shifter Area Dominated by Wiring

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 35 4x4 barrel shifter Width barrel ~ 2 p m M