© Digital Integrated Circuits 2nd Inverter Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Digital Circuits The Inverter

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Outline The transistor as a switch Overview The Inverter: Basics Transfer Characteristics Propagation Delay Inverter Sizing Power Consumption

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB The Transistor as a switch

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Switches

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Switches

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Switches

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Overview

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB The Inverter V DD

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB DC Operation Voltage Transfer Characteristic V(x) V(y) V OH V OL V M V IH V IL f V(y)=V(x) Switching Threshold VOH = f(VOL) VOL = f(VOH) VM = f(VM) Nominal Voltage Levels

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Mapping between analog and digital signals V IL V IH V in Slope = -1 V OL V OH V out “0” V OL V IL V IH V OH Undefined Region “1”

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Definition of Noise Margins Noise margin high Noise margin low V IH V IL Undefined Region "1" "0" V OH V OL NM H L Gate Output Gate Input

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Noise Immunity Noise margin measures the capability of a circuit to overpower a noise source Noise immunity expresses the ability of a system to process and transmit correctly in the presence of noise:  Good noise immunity, input-output noise transfer function is less than 1

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Regenerative Property (a) A chain of inverters. v 0, v 2,... v 1, v 3,...v 1, v 3,... v 0, v 2,... (b) Regenerative gate f(v) finv(v) f(v) (c) Non-regenerative gate v 0 v 1 v 2 v 3 v 4 v 5 v 6...

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Key Reliability Properties Absolute noise margin values are deceptive  a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage) Noise immunity is the more important metric – the capability to suppress noise sources  Key metrics: Noise transfer functions, Output impedance of the driver and input impedance of the receiver;

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Fan-in and Fan-out N Fan-out N Fan-in M M

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB The Ideal Gate R i =  R o = 0 Fanout =  NM H = NM L = V DD /2 g =  V in V out

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Delay Definitions

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Delay depends on technology and topology but also on input and output signals slopes !!! Fall and rise times apply to individual waveforms. They are largely defined by the strength of the driving gate and the load The de facto standard circuit for delay measurement is the ring oscillator

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Ring Oscillator

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB A First-Order RC Network v out v in C R t p = ln (2)  = 0.69 RC; tr = 2.2 RC Important model – matches delay of inverter

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB The Inverter: Basics

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB The CMOS Inverter: A First Glance V in V out C L V DD

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB CMOS Inverter Polysilicon In Out V DD GND PMOS 2 Metal 1 NMOS Contacts N Well

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB CMOS Inverter First-Order DC Analysis V OL = 0 V OH = V DD V M = f(R n, R p ) V DD V V in 5 V DD V in 5 0 V out V R n R p

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Voltage Transfer Characteristics V DSp I Dp V GSp =-2.5 V GSp =-1 V DSp I Dn V in =0 V in =1.5 V out I Dn V in =0 V in =1.5 V in = V DD +V GSp I Dn = - I Dp V out = V DD +V DSp V out I Dn V in = V DD +V GSp I Dn = - I Dp V out = V DD +V DSp

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB CMOS Inverter Load Characteristics

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB CMOS Inverter VTC

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB The Switching Threshold Switching threshold V M is defined as the point where Vin = Vout

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Switching Threshold as a function of Transistor Ratio Switching threshold V M is defined as the point where Vin = Vout Yielding V M as a function of transistor geometries, threshold voltages and Vdd

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Transistor Ratio Setting Switching threshold V M is defined as the point where Vin = Vout With V M = Vdd/2 the right hand side equals, in general to 1, so that P transistor wider than N for equal margins

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Switching Threshold

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Switching Threshold as a function of Transistor Ratio: Short channel

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Switching Threshold as a function of Transistor Ratio V M is relatively insensitive to variations in device ratio.  Example: 0.25  m (2.4V) process, setting Sn/Sp to 3, 2.5 and 2 yields VM of 1.22, 1.18, 1.13 Asymmetrical characteristics: lot of sizing to obtain a significant shift.  Previous example, Sn/Sp=10 is required to go to 1.5V. Further increases are prohibitive

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Noise Margins

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Determining V IH and V IL V OH V OL V in V out V M V IL V IH A simplified approach

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Inverter Gain Gain is almost purely specified by technology parameters, especially, and in minor way, by Vdd and the transistor sizes

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Inverter Gain (Short Channel) Gain is almost purely specified by technology parameters, especially, and in minor way, by Vdd and the transistor sizes

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Gain as a function of VDD Gain=-1

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Impact of Process Variations V in (V) V out (V) Good PMOS Bad NMOS Good NMOS Bad PMOS Nominal Simulations for standard worst case conditions

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Gain as a function of VDD Reducing power supply reduces power consumption, but it is detrimental to the delay of the gate DC characteristics becomes sensitive to variations Scaling the supply means reducing signal swing. This typically helps to reduce internal noise, but also makes the circuits more sensitive to noise sources that do not scale

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Transient Analysis

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Transient Analysis One method is to obtain an equivalent resistance for the transistor while it is switching The input is assumed to change instantaneously Result varies slightly depending on the model assumed  a) Long channel  b) Short channelShort channel

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Fall time analysis

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Fall time analysis

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Fall time analysis

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Fall time analysis

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Rise time analysis

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Gate delay estimation

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Circuit delay estimation

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Simplifying the problem

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Computing Reff

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB NMOS transistor, logic 0

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB NMOS transistor, logic 0

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB NMOS transistor, logic 1

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB NMOS transistor, logic 1

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB PMOS transistors

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Example of the process

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Cascades

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Cascades

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Equivalent output resistance: Short channel Integrar la curva hasta Vdsat utilizando I D V DS V GS = V DD V /2V DD

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Equivalent switching resistance Resistance is inversely proportional to W/L For Vdd bigger than V T +Vdsat/2, R becomes independent of the supply voltage  Limit value: If supply voltage approaches V T resistance increases dramatically AMI 0.5um; S=3; K=54e-6; Ec L = 0.9V V T = 0.5V Vt Vdsat

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Qualitative Analysis Response dominated by the output capacitance A fast gate has small output C or small resistance (increase W/L) Notice that output resistance of the switch is not constant !!

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB (CMOS) Important Properties High and low levels are VDD and GND (high noise margins) Logic levels are independent of device sizes (ratioless) Steady-state finite resistance path between VDD or GND and output (low output resistance) Zero DC input current: A single inverter can theoretically drive an infinite number of gates … No steady-state direct current path between VDD and GND (no static power consumption)

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Design for Performance

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Computing capacitances: Input (GD) Cgd by Miller appears a 2Cgd at the input and the output Also Cgs and Cgd Wiring (include if noticeable) Assuming M1 and M2 are saturated Cg=Cgs=2/3 WLCox

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Computing capacitances: Output (GD) overlap at the output due to Miller (DB) Drain Diffusions  Cdb has to be linearized Wiring

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Computing capacitances: Inverter Load Fan out capacitance:  M3/M4 do not change mode until Vout reaches 50% (Vout2 is constant). No Miller  Cox changes (one saturated and one in cut-off). It is approximated for the worst case (10% error)

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Example Minimum size inverter in 0.25µm  NMOS: 3λ/2λ (0.375/0.25); PMOS: 9λ/2λ (1.125/0.25) Capacitances:  Cgs on =0.115fF; Cgd on =0.115fF;  Cgs op =0.305fF; Cgd op =0.305fF;  Cdb n =0.8fF; Cdb p =1.35fF;  WLCox n =0.53fF; WLCox p =1.67fF; Inverter capacitances  Cin=2.72fF  Cout=2.68  CL=3.04fF 2.72 fF 5.72 fF

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Computing Capacitances: Pass Transistor From the gate:  If output does not change Cg=Cgso+Cgdo+WLCox Triode  If output changes Cg=Cgso+2Cgdo+(2/3) WLCox  Cav=Cgso+1.5 Cgdo+1.5 WLCox From the S/D terminal  If gate is ON 1 ->0: Cin=Cgso+Cdiff+(2/3) WL Cox  During the transition the transistor is in saturation and we drive the source 0->1: Cin=Cgso+Cdiff  During the transition the transistor is in saturation and we drive the drain  If gate is OFF Cin=Cgso+Cdiff

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Design for Performance Keep capacitances (internal, interconnect and fan-out) small by good layout Increase transistor sizes  watch out for self-loading! Once that the intrinsic capacitance dominates the delay, W/L does not help anymore Increase V DD (????):  There are limits to the maximum.  Increases power consumption

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Delay as a function of V DD The shape of this curve is the same as R vs. VDD Smaller VDD implies smaller current Id, and slower transition

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB If a symmetrical characteristic is not important, inverter can be optimized for speed by reducing the P-size. Design variable: NMOS/PMOS ratio tpLH tpHL tp  = W p /W n If Cw<<C, then optimum factor is sqrt(r) instead of r (symm. swing) Considering two identical cascaded inverters:

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Device Sizing Assuming a symmetrical inverter, the capacitance is composed of: Cint is the self-load, associated with diffusion and gate-drain (Miller) Cext is extrinsec, load, wiring, etc. Whereis the intrinsec delay (Cext=0) What are the consequences of scaling ?

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Device Sizing Cint scales with size ratio S, and also Req: The delay is: The intrinsic delay is independent of sizing and is determined by technology and layout. Making S infinitely large gives the maximum performance gain, eliminating the impact of an external load. Yet, a big enough sizing produces similar results with a gain in Silicon area A big inverter has big input capacitance and affects the previous stages !

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Device Sizing (for fixed load) Self-loading effect: Intrinsic capacitances dominate

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Inverter Chain Sizing

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Inverter Chain CLCL If C L is given: - How many stages are needed to minimize the delay? - How to size the inverters? May need some additional constraints. In Out

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Inverter Delay Minimum length devices, L Assume the same electrical characteristics  Wn = 2 Wp  approx. equal rise tpLH and fall tpHL delays t pHL = k R N C L t pLH = k R P C L Delay (D): 2W2W W

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Delay Formula C int =  C gin with   1 f = C L / C gin - effective fanout Delay is only a function of the ratio between its external load capacitance and its input capacitance Inverter 0.25µm γ=2.68/2.72=0.98

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Apply to Inverter Chain CLCL InOut 12N t p = t p1 + t p2 + …+ t pN

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Optimal Tapering for Given N Delay equation has N - 1 unknowns, C gin,2 – C gin,N Minimize the delay, find N - 1 partial derivatives Result: C gin,j+1 /C gin,j = C gin,j /C gin,j-1 - each stage has the same effective fanout (C out /C in ) - each stage has the same delay Size of each stage is the geometric mean of two neighbors

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Optimum Delay and Number of Stages When each stage is sized by f and has same eff. fanout f: Minimum path delay Effective fanout of each stage:

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Example C L = 8 C 1 In Out C1C1 1ff2f2 C L /C 1 has to be evenly distributed across N = 3 stages:

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Optimum Number of Stages For a given load, C L and given input capacitance C in Find optimal sizing f f that minimizes total delay results from:

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Optimum Effective Fanout f Optimum f for given process defined by g f opt = 3.6 for  =1 For  = 0, f = e, N = lnF

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Trade-offs in the choice of N Number of stages large, intrinsic delay dominates Too small, the effective fan-out dominates With more stages (smaller f), N grows exponencially and f decreases linearly: tp increases With fewer stages (bigger f), N reduces and f increases: tp remains roughly constant

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Choice of N: Example Example: Ci=1fF, Cout=1pF: F=1000 t p (normalized delay) N (number of stages) f f Make f slightly larger than optimum (to round off stages. Typ.=4)

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Normalized delay function of F Values of tp/Optimum(tp) for several designs FUnbufferedTwo StageInverter chain ,00010,

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Buffer Design Nft p

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Impact of Rise Time on Delay

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Practical Rules Keep signal rise times smaller than or equal to gate propagation delays (for both performance and power consumption) Keep rise and fall times small and of similar values (challenge known as slope engineering)

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Power Dissipation

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Where Does Power Go in CMOS? Dynamic Power Consumption Short Circuit Currents Leakage Charging and Discharging Capacitors Short Circuit Path between Supply Rails during Switching Leaking diodes and transistors

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Dynamic Power Dissipation VinVout C L Vdd

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Dynamic Power Dissipation Energy/transition = C L * V dd 2 Power = Energy/transition *f =C L * V dd 2 * f Need to reduce C L, V dd, andf to reduce power. VinVout C L Vdd Not a function of transistor sizes! Dependence with supply voltage is quadratic !!!

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Node Transition Activity and Power

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Short Circuit Currents I peak is a function of transistor sizes. Reading Material CMOS Circuit Speed and Buffer Optimization Hedenstierna, N.; Jeppson, K.O.; Computer-Aided Design of Integrated Circuits and Systems, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on IEEE Transactions on Volume 6, Issue 2, March 1987 Page(s): It is also a strong function of the input and output slopes …

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Short Circuit Currents If the output is too slow, then the P transistor is off and there’s no direct current VinVout C L Vdd

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Short Circuit Current If the output is too fast, then the P transistor goes quickly to saturation (Vds = Vcc) and power consumption is maximum VinVout C L Vdd

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Short Circuit Current Graph of direct current versus output capacitance Short circuit current goes to zero if tfall >> trise, but can’t do this for cascade logic, so...

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB How to keep Short-Circuit Currents Low? Graph of power dissipation versus output capacitance for various rise times (fixed freq. and Vdd)

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Minimizing Short-Circuit Power Vdd =1.5 Vdd =2.5 Vdd =3.3

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Leakage Sub-threshold current one of most compelling issues in low-energy circuit design!

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Reverse-Biased Diode Leakage JS = pA/  m2 at 25 deg C for 0.25  m CMOS JS doubles for every 9 deg C!

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Subthreshold Leakage Component

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Static Power Consumption Wasted energy … Should be avoided in almost all cases, but could help reducing energy in others (e.g. sense amps)

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Energy and Energy-Delay Power-Delay Product (PDP) = E = Energy per operation = P av  t p Energy-Delay Product (EDP) = quality metric of gate = E  t p

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Power Delay Product or Energy/Operation The PDP is a measure of Energy Assuming that the gate is switched at the maximum possible rate of PDP gives the average energy per switching event

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Energy-Delay Product (EDP) PDP is questionable as a performance index. A low supply gives a reduced PDP but at the cost of speed. EDP measures energy and performance: Energy Vdd Energy-Delay Delay

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Principles for Power Reduction Prime choice: Reduce voltage!  Recent years have seen an acceleration in supply voltage reduction  Design at very low voltages still open question (0.6 … 0.9 V by 2010!) Reduce switching activity Reduce physical capacitance

© Digital Integrated Circuits 2nd Inverter Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Appendix Short Channel model

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Short Channel Model Short channel model Vdsat is no longer Vgt=Vg-Vt, but: For small Vgt, Vdsat=Vgt and coincides with the long channel case For bigger drives (Vgt), Vdsat reaches a limit value of Vdsat=Ec L

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Triode and saturation region triode Id Vds Vel. saturation Ec L

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Transfer characteristic cuadratic linear Asymptote: Vt+EcL/2 Id Vg

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB Digital case For the digital case, Vgt is generally big, therefore: Referencias:  Sodini C. G., P. Ko, J. L. Moll, “The effect of high fields on MOS device and circuit performance,” IEEE Trans. El. Devices, Vol. ED31, No. 10, Oct. 1984, pp  Toh K., Ko P., Meyer R. G., “An engineering model for short-channel MOS devices,” IEEE J. Solid state circuits, Vol. 23, No. 4. August 1988, pp