Digital Logic Design Review Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office: Ahmad Almulhem, KFUPM 2010

Objectives Logic Circuits Combinational Sequential Ahmad Almulhem, KFUPM 2010

Introduction Digital circuits have two classes: Combinational Circuits Sequential Circuits Combinational circuits consist of logic gates with inputs and outputs The outputs at any instance of time depend only on the combination of the input values based on logic operations such as AND, OR etc. Sequential circuits, in addition to inputs and outputs also have storage elements, therefore the output depends on both the current inputs as well as the stored values Ahmad Almulhem, KFUPM 2010

Combinational Circuits Ahmad Almulhem, KFUPM 2010 Combinational Circuits.. Input X Output Z Z = F(X) In combinational circuits, the output at any time is a direct function of the applied external inputs..

Design Procedure of Combinational Circuits Ahmad Almulhem, KFUPM 2010 Circuit Specification Truth Table How many input/output? Logic Diagram Minimization K-maps, Algebraic Manipulation. Computer based tools

Logic Gates Ahmad Almulhem, KFUPM 2010 AND OR NANDNOR XOR XNOR NOT

Physical Properties of Gates Building blocks of digital circuits Built using integrated circuits Integrated circuits themselves are built using various technologies. E.g. TTL, CMOS Physical characteristics of an Integrated Circuit depend on the underlying technology Key characteristics of ICs are: Physical voltage ranges for 1 and 0 Gate propagation delay/speed Fan-in and Fan-out Buffers Tri-state Drivers Ahmad Almulhem, KFUPM 2010

Voltage Levels Logic values of 0 & 1 are represented in electrical terms using a voltage level A range of voltage defines logic 0 and logic 1. Any value outside this range is invalid. +5V +0V Illegal Voltage Range Ahmad Almulhem, KFUPM 2010

Propagation Delay The delay when the voltage signal arrives at the input of a circuit, and when the output of the circuit changes, is called the propagation delay A circuit is considered to be fast, if its propagation delay is small (ideally as close to 0 as possible) Delay between input (X, Y) and change in output Z XYXY Z Ahmad Almulhem, KFUPM 2010

Timing Diagram The inputs to a circuit can be changed over time. The timing diagram shows the values of the input signals to a circuit with the passage of time, in the form of a waveform It also shows a waveform for the output XYZXYZ Propagation Delay of the Circuit = τ Inputs Output Timing Diagram for an AND gateTime Ahmad Almulhem, KFUPM 2010

Fanin Fanin of a gate is the number of inputs to the gate For a 3-input OR gate, the fanin = 3 There is a limitation on the fanin for any gate In CMOS IC technology, higher fanin implies slower gates (higher propagation delays) TTL IC gates can have higher fanin

Fanout Fanout is the number of gates that can be driven by a driver gate The driven gate is called the load gate There is a limit to the number of load gates that can be driven by a driver gate Fanout = 3 Ahmad Almulhem, KFUPM 2010

Buffers Buffers have a single input and a single output, where output = input Buffers help increase the drive capability of a circuit by increasing the fanout Ahmad Almulhem, KFUPM 2010

Gates with Tristate outputs These gates have an additional input signal called the Enable This signal (Enable) if high, implies that inputs are accepted by the gate, and outputs are generated If Enable = 0, the gate is in a high impedance state, and the output is disabled Enable EXZ High Z 01 Ahmad Almulhem, KFUPM 2010

Decoder Information is represented by binary codes Decoding - the conversion of an n-bit input code to an m-bit output code with n <= m <= 2 n such that each valid code word produces a unique output code Circuits that perform decoding are called decoders A decoder is a minterm generator Ahmad Almulhem, KFUPM n inputs2 n outputs n-to-2 n Decoder

Decoder (Uses) Decode a 3-bit op-codes:Home automation: Ahmad Almulhem, KFUPM to-8 Decoder Add Sub And Xor Not Load Store Jump op0 op1 op2 2-to-4 Decoder Light A/C Door Light-A/C C0C1C0C1 Load a Add b Store c.

Decoder-Based Combinational Circuits (Example) Ahmad Almulhem, KFUPM 2010 Src: Mano’s book XYZCS S = ∑m (1,2,4,7) C = ∑m (3,5,6,7) 3 inputs and 8 possible minterms 3-to-8 decoder can be used for implementing this circuit

Encoder Encoding - the opposite of decoding - the conversion of an m- bit input code to a n-bit output code with n  m  2 n such that each valid code word produces a unique output code Circuits that perform encoding are called encoders An encoder has 2 n (or fewer) input lines and n output lines which generate the binary code corresponding to the input values Typically, an encoder converts a code containing exactly one bit that is 1 to a binary code corresponding to the position in which the 1 appears n outputs 2 n inputs 2 n -to-n Encoder Ahmad Almulhem, KFUPM 2010

Multiplexers Is a combinational circuit Has a single output Directs one of 2 n input to the output Input to output direction is done based on a set of n select bits Ahmad Almulhem, KFUPM n inputs n select lines one output 2 n x 1 MUX

MUX-based Design (n-1 Select lines) Ahmad Almulhem, KFUPM 2010 ABCF 0000 F = C F = C’ F = F = D0D1D2D3D0D1D2D3 F S1S1 S0S0 A B C C’ 0 1 F(A,B,C)=∑(1,3,5,6)

Combinational vs Sequential A combinational circuit: At any time, outputs depends only on inputs Changing inputs changes outputs No regard for previous inputs No memory (history) Time is ignored ! Ahmad Almulhem, KFUPM 2010 Combinational Circuits inputs X outputs Z

Combinational vs Sequential A sequential circuit: outputs depends on inputs and previous inputs Previous inputs are stored as binary information into memory The stored information at any time defines a state next state depends on inputs and present state Ahmad Almulhem, KFUPM 2010 Combinational Circuits inputs X outputs Z Memory next state present state

Examples of sequential systems Ahmad Almulhem, KFUPM 2010 Traffic lightVending machine ATM What is common between these systems?

Types of Sequential Circuits Two types of sequential circuits: Synchronous: The behavior of the circuit depends on the input signal values at discrete intervals of time (also called clocked) Asynchronous: The behavior of the circuit depends on the order of change of the input signals at any instance of time (continuous) Ahmad Almulhem, KFUPM 2010

Design of Synchronous Sequential Circuits Obtain a state diagram State reduction if necessary Obtain State Table State Assignment Choose type of flip-flops Use FF’s excitation table to complete the table Derive state equations Use K-Maps Obtain the FF input equations and the output equations Draw the circuit diagram Ahmad Almulhem, KFUPM 2010

Building a Sequential Circuit Combinational part Memory Latches Flip-Flops Ahmad Almulhem, KFUPM 2010

Flip Flops Sheet (Mano’s Textbook) Ahmad Almulhem, KFUPM 2010

Registers A register is a group of flip-flops. An n-bit register is made of n flip-flips and can store n bits A register may have additional combinational gates to perform certain operations Ahmad Almulhem, KFUPM …n-1

4-Bit Register A simple 4-bit register can be made with 4 D-FF Common Clock At each positive-edge, 4 bits are loaded in parallel Previous data is overwritten Common Clear Asynchronous clear When Clear = 0, all FFs are cleared; i.e. 0 is stored. Ahmad Almulhem, KFUPM 2010

4-bit Shift Register A simple 4-bit shift register can be made with 4 D-FF Common Clock At each positive-edge, 1 bit is shifted in Rightmost bit is discarded Which direction this register is shifting? Ahmad Almulhem, KFUPM 2010

Universal Shift Register (cont.) Ahmad Almulhem, KFUPM 2010

Ripple Counters Instead of having a common clock signal to all Flip Flops, in a Ripple counter the output of one stage (Flip Flop) is connected to the clock input of the next stage T or JK flip flops are used for this construction because of their capability to flip their stored bits Clock is connected to the least significant bit Flip flops are negative edge-triggered (clock is bubbled) – are active when the clock signal is falling (high to low) Flip flops invert their stored bits, when the input clock signal goes from high (1) to low (0) Ahmad Almulhem, KFUPM 2010 J C Q Q’K R J C Q K R J C Q K R J C Q K R clock pulses Q0Q0 clear’ Q1Q1 Q2Q2 Q3Q3 Logic 1

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