© 2003 Xilinx, Inc. All Rights Reserved HDL Co-Simulation

HDL Co-Simulation © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only After completing this module, you will be able to: Objectives Identify the blocks necessary for HDL Co-Simulation Describe the steps involved in performing HDL Co-Simulation

HDL Co-Simulation © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Introduction Co-Simulation Support Blocks –Black Box –Simulation Multiplexer –ModelSim HDL Co-Simulation Process

HDL Co-Simulation © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only HDL Co-simulation Supports Legacy Code Being able to include legacy code is essential for many DSP system designers Legacy (or new) HDL code can be imported into Simulink –New “black box” function allows designers to import legacy HDL code –Legacy code can be simulated in Simulink to significantly reduce development time HDL is co-simulated transparently –Legacy HDL simulated using industry-standard ModelSim tool from Mentor Graphics directly from Simulink framework Single HDL simulator for multiple black boxes The time scale in ModelSim matches that in Simulink

HDL Co-Simulation © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only HDL Co-simulation Using Black Box Legacy HDL ModelSim Simulator Real-Time Verification

HDL Co-Simulation © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Introduction Co-Simulation Support Blocks – Black Box – Simulation Multiplexer – ModelSim HDL Co-Simulation Process

HDL Co-Simulation © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only HDL Co-Sim Support Blocks System Generator libraries provide both high-level and basic functions for building systems However, designers may have IP blocks or needs for building one with their own HDL modules which must be simulated in conjunction with other System Generator libraries blocks Supported blocks to perform HDL co-simulation – Black Box block – ModelSim block – Simulator Multiplexer block Black Box block provides an interface between the Simulink model and structural HDL source code ModelSim block provides a means to invoke ModelSim simulator and data exchange between Simulink simulator and ModelSim simulator

HDL Co-Simulation © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Black Box Block Provides a way to incorporate hardware description language (VHDL or Verilog) models into System Generator The block is used to specify both the simulation behavior in Simulink and the implementation files to be used during code generation with System Generator Assumes the interface (ports and parameters) of the function it implements, and its ports produce and consume the same sorts of signals as other System Generator blocks Black box HDL code can be co-simulated with Simulink using the System Generator interface to the ModelSim simulation software from Model Technology, Inc.

HDL Co-Simulation © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Black Box Requirements An HDL component associated with a black box must adhere to the following System Generator requirements and conventions –The entity name must not collide with any other entity name in the design –Bi-directional ports are not allowed on the top-level black box entity –For Verilog black boxes, the module and port names must be lower case and must follow standard Verilog naming conventions –Any port that is not a clock or clock enable must be of type std_logic_vector (For Verilog black boxes, ports must be of vector type, e.g., input[3:0] din; input [0:0] dout) –Any port that is a clock or clock enable must be of type std_logic. (For Verilog black boxes, ports must be of non-vector inputs, e.g., input clk) Top-level HDL must have a separate clock and clock enable port for each associated sample rate in Simulink

HDL Co-Simulation © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Black Box Requirements Clock and clock enable ports in black box HDL should be expressed as follows –Clock and clock enables must appear as pairs (i.e., for every clock, there is a corresponding clock enable, and vice-versa) –Although a black box may have more than one clock port, a single clock source is used to drive each clock port –Only the clock enable rates differ –Each clock name (and clock enable name) must contain the substring clk (and ce) –The name of a clock enable must be the same as that for the corresponding clock, but with ce substituted for clk For example, if the clock is named src_clk_1, then the clock enable must be named src_ce_1 Clock and clock enable ports are not visible on the black box block icon

HDL Co-Simulation © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Black Box M-Configuration File A black box must describe its interface through a MATLAB m-function –e.g., ports and generics, and its implementation, and optionally, its simulation model through an HDL co-simulator The name of this function must be specified in the block parameter dialog box under the Block Configuration M-Function parameter The configuration m-function does the following –Specifies the top-level entity name of the HDL component that should be associated with the black box –Selects the language (i.e., VHDL or Verilog) –Describes ports, including type, direction, bit width, binary point position, name, and sample rate –Defines any generics required by the black box HDL –Specifies the black box HDL and other files (e.g., EDIF) that are associated with the block –Defines the clocks and clock enables for the block –Declares whether the HDL has any combinational feed-through paths

HDL Co-Simulation © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Configuration-M File Following section shows the function definition and top-level block entry, and also shows the added entries, which the top-level requires to successfully compile in ModelSim simulator function fir_blackbox_config(this_block) % Revision History: % % 11-Jul-2003 (13:14 hours): % Original code was machine generated by Xilinx's System Generator after parsing % C:\training\dsp_flow\labs\lab5\fir_blackbox.vhd % this_block.setTopLevelLanguage('VHDL'); this_block.addFile('fir.edn'); -- added entries this_block.addFile('fir.mif'); this_block.addFile('fir.vhd'); this_block.setEntityName('fir_blackbox');

HDL Co-Simulation © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Configuration-M File Additional code which defines if the model has combinatorial path. It also defines input and output ports and width for a port that is more than one bit wide this_block.tagAsCombinational; this_block.addSimulinkInport('reset'); this_block.addSimulinkInport('din'); this_block.addSimulinkOutport('dout'); dout_port = this_block.port('dout'); dout_port.setType('Fix_30_0');

HDL Co-Simulation © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Configuration-M File Next, inputs are checked for name and corresponding widths if (this_block.inputTypesKnown) % do input type checking and dynamic output type and generic settup in this code block. if (this_block.port('reset').width ~= 1); this_block.setError('Input data type for port "reset" must have width=1.'); end if (this_block.port('din').width ~= 12); this_block.setError('Input data type for port "din" must have width=12.'); end end % if(inputTypesKnown) if (this_block.inputRatesKnown) setup_as_single_rate(this_block,'input_clk','input_ce') end % if(inputRatesKnown) %

HDL Co-Simulation © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Black Box Block Parameters Specifies the name of the configuration m-function that is associated to the black box Tells the mode (Inactive or Use HDL Co-Simulation) to use for simulation – When the mode is Inactive, the black box ignores all input data and writes zeroes to its output ports –Usually for this mode the black box should be coupled, using a Simulation Multiplexer block, with a parallel simulation model Indicates helperblock to be used during HDL Co-Simulation

HDL Co-Simulation © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Simulation Multiplexer The Simulation Multiplexer is a System Generator block that allows two portions of a design to work in parallel, with simulation results provided by the first portion and hardware providing the second –This is useful when a subsystem is defined in the usual way with Simulink blocks, but black box HDL is used to implement the subsystem in hardware OR black box HDL is used with HDL Co-Simulator and the Simulator is made inactive –Another use for the multiplexer is to switch between black boxes that incorporate different types of HDL. One might provide behavioral HDL to be used in simulation, and the other might provide RTL to be used for implementation

HDL Co-Simulation © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Simulation Multiplexer Block Parameters For Simulation, Pass Through Data from Input Port : Determines which input port (either 1 or 2) is used for simulation For Generation, Pass Through Data from Input Port : Determines which input port (either 1 or 2) is used for generation

HDL Co-Simulation © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only ModelSim Block The ModelSim HDL co-simulation block configures and controls co-simulation for one or several black boxes The block does the following –Constructs the additional VHDL needed to allow black box HDL to be simulated inside ModelSim –Spawns a ModelSim session when a Simulink simulation starts –Mediates the communication between Simulink and ModelSim –Reports whatever errors are detected when black box HDL is compiled –Terminates ModelSim, if appropriate, when the simulation is complete During a simulation, each ModelSim block spawns one copy of ModelSim, and therefore uses one ModelSim license If licenses are scarce, several black boxes can share the same block. Except for minor reductions in flexibility, nothing is lost with this approach The time scale in ModelSim matches that in Simulink, i.e., one second of Simulink simulation time corresponds to one second of ModelSim simulation time

HDL Co-Simulation © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only ModelSim Block Parameters ModelSim is started in the directory named by this field –The directory is created if necessary –The directory can be specified as an absolute or relative path When this checkbox is selected, the ModelSim waveform window opens automatically, displaying a standard set of signals When this checkbox is selected, the ModelSim session is left open after the Simulink simulation has finished To specify the script, select Add Custom Scripts and enter the script name (e.g., myscript.do) in the Script to Run After vsim field

HDL Co-Simulation © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline Introduction Co-Simulation Support Blocks –Black Box –Simulation Multiplexer –ModelSim HDL Co-Simulation Process

HDL Co-Simulation © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only HDL Co-Simulation (Step I) Drag a Black Box into the model Configuration Wizard detects VHDL files & customizes block

HDL Co-Simulation © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only HDL Co-Simulation (Step II) Drag a ModelSim block into the model Select ModelSim Simulation Mode

HDL Co-Simulation © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only HDL Co-Simulation (Step III) Select ModelSim Simulation Mode Simulink opens ModelSim and co-simulates

HDL Co-Simulation © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Stage 2: Cost Reduction Your demanding manager has asked you to investigate other techniques for creating a smaller filter as the complete design utilization (including other functions in the chip) of the prototype is too big. A 50% slice reduction should enable the complete design to fit in a small Spartan-IIE or Spartan™-3 device. This would provide the product with a significant price reduction and give it the competitive edge required to dominate the market. Also if you could exploit the Embedded multipliers that would be beneficial as the rest of the system will be not be using these and your manager does not want to waste resources. The filter specs are still the same: Band Pass Filter Sampling Frequency (Fs) = 1.5 Mhz Fstop 1 = 270 Khz Fpass 1 = 300 Khz Fpass 2 = 450 Khz Fstop 2 = 480 Khz Attenuation on both sides of the passband = 54dB Pass band ripple = 1 Data Bit Width = 8 Bits Coefficient Bit Width = 12 Bits

HDL Co-Simulation © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Lab 5 Simulate a MAC FIR filter core through ModelSim invoked from System Generator and verify the functionality Incorporate a core as a black box into your design and simulate your design using HDL co-simulation with ModelSim simulator Understand how to build an interface between the black box and MATLAB configuration file Use the black box in a different way to bring the core into Simulink via Hardware co-simulation and observe the improvement in verification speed