Heng Tan Ronald Demara A Device-Controlled Dynamic Configuration Framework Supporting Heterogeneous Resource Management

Previous Work - Tool Level Approach Device Supported On-chip System Bit Stream Reuse Potential Limitations Moraes, Mesquita, Palma, Moller Virtex XCV300 devices NoN Lack of area Relocation Raghavan, Sutton Xilinx Virtex devices NoN Cumbersome CAD flow Blodget, McMillan Virtex II devices PartialYes Direct bit stream reuse required

Proposed Work: Multilayer Runtime Reconfiguration Architecture (MRRA) Develop MRRA fast reconfiguration paradigm for the CRR approach Validate with real hardware platform along with detailed performance analysis Serve as the first general-purpose framework for a wide variety of applications that require reconfiguration process during operation Extend existing theories on reconfiguration

Loosely Coupled Solution The entire system operates on a 32-bit basis The Virtex-II Pro is mounted on a development board which can then be interfaced with a WorkStation running Xilinx EDK and ISE.

LCS Implementation Resource name Number of Available Number of Used Utilization IOBs % Slices % BRAM244454% TBUFs % PPC % BUFGMUXs4125%

APIs on Host PC API nameInput ParameterOperationData Width Initial N/A Recognizes and Initializes the FPGA board N/A WriteBitFile char Filename[] Reads configuration file from the board and writes to Host PC File length ReadBitFile char Filename[] Reads the configuration file from the Host PC and writes to the FPGA board File length ByteRead unsigned long StartAddr, unsigned long EndAddr, int AccessBar Reads the on board memory8 bits WordRead unsigned long StartAddr, unsigned long EndAddr, int AccessBar Reads the on board memory16 bits DWordRead unsigned long StartAddr, unsigned long EndAddr, int AccessBar, unsigned long AccessData Reads the on-board memory 32 bits ByteWrite unsigned long StartAddr, unsigned long EndAddr, int AccessBar, unsigned long AccessData Writes to the on-board memory8 bits WordWrite unsigned long StartAddr, unsigned long EndAddr, int AccessBar, unsigned long AccessData Writes to the on-board memory16 bits DWordWrite unsigned long StartAddr, unsigned long EndAddr, int AccessBar, unsigned long AccessData Writes to the on-board memory32 bits

APIs on Chip CPU Core API nameInput ParameterOperationData Width Intc_setup N/A Initializes and enables the interrupt controller N /A DeviceDriverHandler *CallbackRef The corresponding routine for the SRAM ownership request interruption from host PC N/A mem_dump unsigned start_addr, unsigned end_addr Reads the on board and on-chip memory&register 32 bits mem_write unsigned wr_addr, unsigned wr_value Writes the on board and on-chip memory&register 32 bits flash_test unsigned start_addr, unsigned end_addr Thorough validation test on the flash 32 bits mem_test unsigned start_addr, unsigned end_addr Thorough validation test on the flash memory 32 bits

Future Theoretical Work Communication overhead, throughput and overall speed-up analysis Translation Complexity Analysis –The quantity of information that needs to be translated to generate the reconfiguration bitstream –Simplification from file level to bit level is expected Storage Complexity Analysis –The memory space that is required for the run-time algorithms

Resources Utilization Resource name Number of Available Number of Usedutilization IOBs % Slices % BRAM44818% TBUFs % PPC % BUFGMUXs4125%

Overall Design

PR Module

Operational Characteristics Task Task: A function synthesized to a digital circuit in the form of module that can be programmed and downloaded into the reconfigurable device. A task has a size and a shape. TaskModularity Task Modularity: The smallest granularity that this architecture deals with is at task level. The size and shape generate the area requirement of the task in CLBs. General-purpose application scenario General-purpose application scenario: The architecture may carry out an arbitrary number of tasks. There are no predefined constraints on the tasks. The functions of the tasks are also unknown a-priori. Runtime scenario Runtime scenario: The architecture does not know in advance when and what tasks will arrive and what their properties will be. When a task is generated, the system processes it online at runtime.

Issues to Address Partitioning Partitioning: Selecting computational resources to initialize as component Placement Placement: Determining the target location of the component on the reconfigurable fabric of the device Routing Routing: Interfacing the component to its surrounding resources Generation Generation: Generating the bitstream of the component at the target location, and Configuration Configuration: Writing the generated bitstream to the appropriate portions of the underlying reconfigurable infrastructure of the reconfigurable fabric

Routing: Reconfiguration Module Template OPB Addr decoder Slave attach MIR/ Reset User Logic IPIF Reconfigurabl e Module Bus Macro Reconfigurabl e or Fixed Module Reconfiguration module Template Intermodule Signal

Generation: Partial Reconfiguration Flow (Top-Level Design) Design Entry HDL Entry/Synthesis Initial Budgeting (Top-level Design) Design Entry HDL Entry/Synthesis (Module) Active Module Implementation (Module) Mapping Placement Routing Final Assembly (Top-Level Design and Modules) Mapping Placement Routing Download to device