Wing LDA CALICE Collaboration Meeting DESY Hamburg, 21. March 2013 André Welker Lennart Adam, Bruno Bauss, Volker Büscher, Reinhold Degele, Karl Heinz.

Slides:



Advertisements
Similar presentations
Bart Hommels for the CALICE-UK groups Data acquisition systems for future calorimetry at the International Linear Collider Introduction DAQ.
Advertisements

Die folgenden slides werden zur Zeit noch überarbeitet 1 slide pro aktivität Wichtig ist die Information: 1. Motivation: worum geht es? Was sind die Ziele?
– Calice Collaboration Meeting
HEP UCL Cambridge University Imperial College London University of Manchester Royal Holloway, University of London University College London Matthew Warren,
Vincent Boudry Franck Gastaldi Antoine Matthieu David Decotigny CALICE meeting 19 feb Kyungpook Nat'l U., Daegu, Korea Status of the Data Concentrator.
Clock module for TB spring 2012 Uli Schäfer 1 R.Degele, P.Kiese, U.Schäfer, A.Welker Mainz.
Developing the Timepix Telescope Planning a Future Timepix Telescope Richard Plackett – VELO Testbeam Meeting CERN, 7th October 09.
11 May 2007UK DAQ Status1 Status of UK Work on FE and Off-Detector DAQ Paul Dauncey For the CALICE-UK DAQ groups: Cambridge, Manchester, Royal Holloway,
1 Overview of DAQ system DAQ PC LDA ODR Detector Unit DIF CCC Detector Unit DIF Detector Unit DIF Detector Unit DIF Storage Control PC (DOOCS) DAQ PC ODR.
Uli Schäfer 1 JEM1: Status and plans JEM1.1 Status Plans.
Uli Schäfer 1 JEM1: Status and plans power Jet Sum R S T U VME CC RM ACE CAN Flash TTC JEM1.0 status JEM1.1 Plans.
1 Design of the Front End Readout Board for TORCH Detector 10, June 2010.
Update on the Data Acquisition System development in the UK Valeria Bartsch, on behalf of CALICE-UK Collaboration.
CALICE – 12/07/07 – Rémi CORNAT (LPC) 1 ASU and standalone test setup for ECAL MAIA BEE project Overview DAQ dedicated Sensor test In situ debug and maintenance.
EUDET Annual Meeting, Munich, October EUDET Beam Telescope: status of sensor’s PCBs Wojciech Dulinski on behalf.
Mathias Reinecke CALICE meeting Argonne EUDET module – Electronics Integration Contents -Next prototype : architecture -HCAL Base Unit (HBU)
Bart Hommels for the UK-DAQ group Status of DIF, DAQ for SiW Ecal DIF status LDA status DAQ (ODR & software) status CALICE / EUDET DAQ – DESY.
AIDA annual meeting,Vienna, 26th March 2014Václav Vrba, Institute of Physics, Prague 1  design of sensors for production submission  design of the readout.
Status of CCC CALICE Collaboration Meeting DESY Hamburg, 21. March 2013 André Welker Lennart Adam, Bruno Bauss, Volker Büscher, Reinhold Degele, Karl Heinz.
In-Beam PET Status Report -- TPS. 2 TPS project PET monitoring prototype 2D view of the FOV coverage of the 4+4 modules Use of 4 modules vs. 4 modules.
Data Acquisition Systems for Future Calorimetry at the International Linear Collider Matt Warren, on behalf of CALICE-UK Collaboration.
Tuesday September Cambridge1 GDCC “next replacement of the LDA” Franck GASTALDI.
David Cussans, AIDA/CALICE DAQ Palaiseau, 10 Nov 2011 Trigger/Timing Logic Unit (TLU) for AIDA Beam-Test.
Mainz hardware activities - clock module for TB spring R.Degele, P.Kiese,U.Schäfer, A.Welker Mainz Uli Schäfer 1.
CALICE: status of a data acquisition system for the ILC calorimeters Valeria Bartsch, on behalf of CALICE-UK Collaboration.
CaRIBOu Hardware Design and Status
JRA3 DAQ Overview Matt Warren, on behalf of EUDET JRA3 DAQ Groups. Please see the following talks from the JRA3 Parallel Session for more detail: DAQ and.
HBD FEM Overall block diagram Individual building blocks Outlook ¼ detector build.
Status report on the development of a readout system based on the SALTRO-16 chip Leif Jönsson Lund University LCTPC Collaboration Meeting
J. Prast, G. Vouters, Arlington, March 2010 DHCAL DIF Status Julie Prast, Guillaume Vouters 1. Future CCC Use in DHCAL Setup 2. Calice DAQ Firmware Implementation.
Detector Interface (DIF) Status CALICE meeting – DESYDec Mathias Reinecke.
R&D for a 2nd generation AHCAL prototype LCWS 2007 – DESY Hamburg Mathias Reinecke on behalf of the AHCAL partners.
24 Mar 2009Paul Dauncey1 CALICE-UK: The Final Curtain Paul Dauncey, Imperial College London.
CALICE / Silicon PM activities Detector and readout electronics development Development of a system for mass production of AHCAL “HBU” scintillator/PCB.
AHCAL Electronics. Status Commissioning Mathias Reinecke for the AHCAL developers HCAL main meeting Hamburg, Dec. 10th, 2009.
Monday December DESY1 GDCC news Franck GASTALDI.
Towards a 7-module Micromegas Large TPC prototype 1 D. Attié, P. Baron, D. Calvet, P. Colas, C. Coquelet, E. Delagnes, M. Dixit, A. Le Coguie, R. Joannes,
Barcelona 1 Development of new technologies for accelerators and detectors for the Future Colliders in Particle Physics URL.
Connector Differential Receiver 8 Channels 65 MHz 12 bits ADC FPGA Receive/buffer ADC data Format triggered Events Generate L1 Primitives Receive timing.
1 On- and near-detector DAQ work for the EUDET calorimeters Valeria Bartsch, on behalf of CALICE-UK Collaboration.
Julie Prast, Calice Electronics Meeting at LAL, June 2008 Status of the DHCAL DIF Detector InterFace Board Sébastien Cap, Julie Prast, Guillaume Vouters.
AHCAL Electronics. Status and Outlook Mathias Reinecke for the AHCAL developers CALICE Days DESY Hamburg, March 31st, 2009.
ECFA Workshop, Warsaw, June G. Eckerlin Data Acquisition for the ILD G. Eckerlin ILD Meeting ILC ECFA Workshop, Warsaw, June 11 th 2008 DAQ Concept.
Maurice Goodrick, Bart Hommels CALICE-UK Meeting, Cambridge CALICE DAQ Developments DAQ overview DIF functionality and implementation EUDET.
AHCAL Integration. Status and Outlook Mathias Reinecke for the AHCAL developers CALICE week Lyon IPNL, Sept. 16th – 18th, 2009.
Mathias Reinecke CALICE week - Manchester Electronics Integration - Status Mathias Reinecke for the AHCAL developers.
DAQ PC CALICE DAQ architecture Detector Unit : ASICs DIF : Detector InterFace connects Generic DAQ and services LDA : Link / Data Aggregator – fanout /
INSIDE – Update meeting PET DAQ 24 March Refresh from the last meetings Objectives of the PET DAQ – Provide a full in-beam (full-beam) PET system.
1 Update on the project - selected topics - Valeria Bartsch, Martin Postranecky, Matthew Warren, Matthew Wing University College London.
AHCAL Electronics. Status of Integration Mathias Reinecke for the DESY AHCAL developers AHCAL main and analysis meeting Hamburg, July 16th and 17th, 2009.
News from the 1m 2 GRPC SDHCAL collection of slides from : Ch.Combaret, I.L, H.Mathez, J.Prast, N.Seguin, W.Tromeur, G.Vouters and many others.
AHCAL LDA CALICE electronics and DAQ Meeting DESY Hamburg, Dec. 10, 2012 André Welker Bruno Bauss, Volker Büscher, Reinhold Degele, Sascha Krause, Yong.
Backplanes for Analog Modular Cameras EVO meeting. March 14 th,
DHCAL Acquisition with HaRDROC VFE Vincent Boudry LLR – École polytechnique.
Novosibirsk, September, 2017
Progress of Megatile Studies
EUDET Elec/DAQ meeting
Megatile Studies Yong Liu Johannes Gutenberg Universität Mainz
CALICE DAQ Developments
Wing-LDA Timing & performance Beam Interface (BIF)
AHCAL Beam Interface (BIF)
ECAL Integration / CALICE DAQ task force
A New Clock Distribution/Topology Processor Module for KOTO (CDT)
Comments on the DAQv2 advancement
Status of the DHCAL DIF Detector InterFace Board
Testbeam Timing Issues.
SEABAS/EUTelescope Integration Idea
CALICE/EUDET Electronics in 2007
Status of the EUDET Prototype
State of developments on Readout interface of European DHCAL
Presentation transcript:

Wing LDA CALICE Collaboration Meeting DESY Hamburg, 21. March 2013 André Welker Lennart Adam, Bruno Bauss, Volker Büscher, Reinhold Degele, Karl Heinz Geib, Sascha Krause, Yong Liu, Lucia Masetti, Phi Chau, Uli Schäfer, Rouven Spreckels, Stefan Tapprogge, Rainer Wanke

Read-out-chain André Welker, CALICE Collaboration Meeting, DESY, 21. March 2013 SiPMASIC detector interface digital analog HBU data- aggregator (LDA) clock- and control-card (CCC) SiPMASIC detector interface digital analog HBU control clock trigger data busy DAQ PC beam control Ethernet on-detector-electronicoff-detector-electronic Ethernet control, trigger, clock, busy 2 fan-out more LDAs

Read-out-chain André Welker, CALICE Collaboration Meeting, DESY, 21. March 2013 SiPMASIC detector interface digital analog HBU data- aggregator (LDA) clock- and control-card (CCC) SiPMASIC detector interface digital analog HBU control clock trigger data busy DAQ PC beam control Ethernet on-detector-electronicoff-detector-electronic Ethernet control, trigger, clock, busy 2 fan-out more LDAs

Position of the LDA 3 LDA integrated in the 10x10cm cableshaft: André Welker, CALICE Collaboration Meeting, DESY, 21. March 2013 HCAL- /TPC-cabelshaft with coolingpipes ECAL-cableshaft 110cm challenges: problems: LDA outside of the detector  96 cables in the cableshaft solution/problem: 110 cm PCB  timedelay between each layer (up to 5ns) solution: on-board-electronic regulates timing differences 10cm

Position of the LDA 3 LDA integrated in the 10x10cm cableshaft: André Welker, CALICE Collaboration Meeting, DESY, 21. March 2013 HCAL- /TPC-cabelshaft with coolingpipes ECAL-cableshaft 110cm challenges: problems: Pitch between the 48 layers depends on (18/23 mm for W/Fe) solution:  Smallest possible HDMI micro connector Now only - One Ethernet cable - One control cable in the detector 10cm Ethernet-Uplink Control cable CCC

Mechanic and flexibility: LDA with rigid-flex connections: central module right wing left wing 4André Welker, CALICE Collaboration Meeting, DESY, 21. March 2013 Active and Passive LDA consists of 4 parts: 1.Three passive PCBs: The 96 connectors are on these PCBs. 2.One active PCB: it is a daughter module for tests and fast repairs. rigid-flex connection

Wing-LDA The first PCB: 1. Wing with 17 HDMI-connectors routed: 5André Welker, CALICE Collaboration Meeting, Cambridge, Sep. 18, mm old ideas

Wing-LDA The second PCB: 2. Center PCB with 12 HDMI-connectors: 6André Welker, CALICE Collaboration Meeting, Cambridge, Sep. 18, mm DATA/BUSY TRIG/CLK/DATA DATA/BUSY TRIG/CLK/DATA old ideas

LDA Layout Passive PCB: 1. Wing with 32 HDMI connectors: 7 367,5mm André Welker, CALICE Collaboration Meeting, DESY, 21. March mm

LDA Layout Passive PCB: 2. Central module with 32 HDMI connectors: 8 365mm André Welker, CALICE Collaboration Meeting, DESY, 21. March mm

SD FPGA MARS HDMI-CCC RJ45 280mm 80mm LDA Layout Active PCB: 3. Daughter module with 4 FPGAs and a Mars module: André Welker, CALICE Collaboration Meeting, DESY, 21. March 20139

Active PCB: 3. FPGA daughter module mm Zynq André Welker, CALICE Collaboration Meeting, DESY, 21. March 2013 Mars-ZX3 LDA Peculiarity: -Manages 1100 signals and sends them over the Ethernet -Has a Zynq processor who -has implemented an Arm9 dual core (with Linux) -and one FPGA -Same module as CCC Data/BUSY Legend: Control/Trigger/Clock FPGA CCC-Connector Ethernet Data BUSY

2 GeV beam May 2013 Testbeam (DESY) André Welker, CALICE Collaboration Meeting, DESY, 21. March DAQ PC data clock- and control card (CCC) beam control control - Next testbeam with 8 layers at the end of may control busy

LDA Status LDA collects parallel data from 96 detector layers and leads the clock to each of them without a timing delay 80% of the LDA design is finished Order the PCBs in 1 week Firmware will be finished in 1 month Software is finished Ready to readout two full ILD detector segments with 48 layers each 12André Welker, CALICE Collaboration Meeting, DESY, 21. March 2013

Integration of CCC and LDA 1.Read-out data and send slow control data from the HBU layers as before over USB, but integrate the CCC for clock, trigger and busy signals 2.Read-out data by USB but send slow control data, clock, busy, trigger over the CCC 3.Integrate the LDA for data read-out instead of the USB, without interference from us in the regular data acquisition 4.Firmware and software will be written by us, so we don‘t interrupt the manpower on the DIF side 13André Welker, CALICE Collaboration Meeting, DESY, 21. March 2013 Steps:

André Welker, CALICE Collaboration Meeting, DESY, 21. March 2013 Thank you for your attention!