Bus-Driven Floorplanning Hua Xiang*, Xiaoping Tang +, Martin D. F. Wong* * Univ. Of Illinois at Urbana-Champaign + Cadence Design Systems Inc.

Floorplanning & Bus Planning Bus planning An important issue for floorplanning in DSM Buses: Different widths Go through several module blocks The positions of module blocks heavily affect bus planning.

An Example (a) A floorplan with 2 buses. (b) Neither bus can be assigned.

Bus-Driven Floorplanning (BDF) Given: A set of rectangular macro blocks A set of buses Objective: Decide positions of blocks and buses Constraints: No overlap between any two blocks No overlap between any two horizontal (vertical) buses Buses go through all of the related blocks Minimize chip area as well as the total bus area

Preliminary Sequence Pair A pair of sequences of n elements representing a list of n blocks. Block position relationship ( … b i … b j …, … b i … b j … ) ( … b i … b j …, … b j … b i … ) Bus representation

Feasible Buses Feasible Horizontal Bus Bus is feasible  y max – y min ≥ w, where y max = min {y i + h i | i =1, …, k} y min = max {y i | i =1, …, k}

Necessary Condition for One Bus (a) A horizontal bus ( … A … D … B … C …, … A … D … B … C … ) (b) A vertical bus ( … A … C … B …, … B … C … A … )

Necessary Condition for One Bus Theorem 1 (Block Ordering) Given: A sequence pair (X, Y) A bus u = {b 1, b 2, …, b k } If u is feasible The ordering of the k blocks should be either the same or reverse in X and Y. Same order  Horizontal bus Reverse order  Vertical bus

Bus Ordering between Two Buses Given two horizontal buses: u = {a 1, …, a m } and v = {b 1, …, b n } Let S u = {a 1, …, a m }, S v = {b 1, …, b n }. S = S u ∪ S v and L = |S| ( L ≤ m + n ) Given a sequence pair (X, Y) = ( … c 1 … c 2 … … c L …, … d 1 … d 2 … … d L … ) where c i ∈ S and d i ∈ S Subsequence pair: (X ’, Y ’) = ( c 1 c 2 … c L, d 1 d 2 … d L ) Let p[c i ] = i and q[d i ] = i (i = 1, …, L)

Bus Ordering between Two Buses Case 1 ;  bus u is above bus v  Bus Constraint Two buses: {A, B, C} {D, E, F} SubSequence pair (D A E B F C, A D B E C F)

Bus Ordering between Two Buses Case 2 ;  bus u is below bus v  Bus Constraint Two buses: {A, B, C} {B, D, E} SubSequence pair (A D B C E, D A B E C)

Bus Ordering between Two Buses Case 3 (Bus Crossing) ;  u and v can’t be assigned at the same time Two buses: {A, B} {C, D} SubSequence pair (A C D B, C A B D)

Bus Ordering between Two Buses Case 4  No Bus Constraint Two buses: {A, B, C} {D, E} SubSequence pair (A D B E C, A D B E C)

Multiple Bus Ordering The ordering of buses in a BDF solution cannot be a cycle For example: Bus u is above bus v Bus v is above bus w Bus w is above bus u

Bus Ordering Constraint Graph Each bus is represented by a node. If one bus u is above bus v (Case 1 or 2), then add one edge (u, v). If two buses u and v are crossing (Case 3), then two edges (u, v) and (v, u) are added. If two buses have no bus constraint (Case 4), then no edges are added.

Cycles in Constraint Graph A cycle in a bus ordering constraint graph  At least one bus cannot be assigned Two kinds of cycles A cycle caused by bus crossing (Case 3) A cycle caused by multiple buses

Cycles in Constraint Graph (cont) A cycle caused by bus crossing Two buses: {A, B} {C, D} SubSequence pair (A C D B, C A B D)

Cycles in Constraint Graph (cont) A cycle caused by multiple buses Three buses: {A 1, A 2 } {B 1, B 2 } {C 1, C 2 } Sequence pair ( A 1 B 1 B 2 C 1 C 2 A 2, B 1 A 1 C 1 B 2 A 2 C 2 )

Cycles in Constraint Graph (cont) Remove fewest nodes from a constraint graph  The graph contains no cycles It is proved to be an NP-Complete problem. A heuristic approach If a node whose in-degree or out-degree is zero, then the node should not be removed. If all nodes whose in-degree and out-degree are non-zero, remove the node with the max degree.

Node Removal in Constraint Graph (a) A constraint graph with cycles.(b) Nodes a, e and d are good nodes and they are not considered.

Node Removal in Constraint Graph (b) Nodes a, e and d are good nodes and they are not considered. (c) Node c has the max degree and it is removed from the graph.

Node Removal in Constraint Graph (a) A constraint graph with cycles. (d) Nodes c and i are removed to break cycles.

BDF Algorithm Simulated Annealing Perturbation (Move) Cost Function Evaluation Algorithm

Perturbation (Move) Swap Exchange two blocks in the first sequence Exchange two blocks in the second sequence Take constant time Rotation Exchange the width and height of a block No change to the sequence pair Take constant time

Cost Function Objective Fit in all buses Minimize the chip area Minimize the total bus area Cost Function C : the chip area B : the total bus area M : the number of unassigned buses

Evaluation Algorithm Transform a sequence pair to a BDF solution How to detect infeasible buses ? Violate block ordering  Discard the bus Bus nodes form cycles in a constraint graph  Node Removal How to decide block positions ? Longest Common Subsequence Computation (LCS) How to assign buses ? Assign a bus if its related blocks have been processed Related blocks may have to move up/left to meet bus alignment requirement

Bus Assignment Buses are processed from bottom to top one by one Buses are ordered according to bus constraint graph Bus u ={A, B, C} is above v ={E, B, G}. v should be assigned before u.

Bus Assignment (cont) Block alignment for one bus y max = max {y i | i = 1, …, k} y i = max (y i, y max + w – h i ) Bus_Overlap (a) Two buses overlap(b) No overlap between two buses

(b) Blocks appear interlaced. (A D B E C, A D B E C) Bus Assignment (cont) Cases for Bus_Overlap Two buses have ordering constraint (Case 1 or 2), no Bus_Overlap Two buses have no ordering constraint (Case 4), there are 3 cases (a) Two buses share at least one block. (c) Blocks appear non-interlaced. (A B C D E, A B C D E) Bus_Overlap may happen for (a) and (b)

Evaluation Algorithm Evaluation_BDF (seq_pair, buses){ 1. Feasible_Bus_Checking_Orientation // Remove buses which cannot be assigned due to block ordering or // cycles in constraint graphs. At the same time, decide bus orientation 2. Bus_Ordering //Sort buses according to below-above/left-right relationship 3. Modified_lcs_computation //Calculate the positions of blocks and buses 4. Cost_Calculation 5. Return cost }

Soft Block Adjustment Blocks on longest common subsequence paths decide the chip size. Each time, one soft block on a longest common subsequence path is selected, and its width and height are adjusted. Simulated Annealing is applied again to find a compact floorplan.

Soft Block Adjustment (cont) An example Blocks B, D, E are on a critical path. E is selected and adjusted. The chip size is reduced.

Experimental Results Hardware: workstation (2.4GHz) with 1G memory Software: C++ Test files MCNC benchmarks Industry designs Bus grid test files

Experimental Results (cont) (a) MCNC benchmarks FileBlocksBuses Packing ResultsSoft Block Adjustment Time(s)DeadspaceTime(s)Deadspace apte %12 (+1)0.72% xeorx %13 (+1)0.95% hp %28 (+0)0.62% ami %62 (+1)0.94% ami %86 (+5)1.27% ami %101 (+3)0.85% ami %281 (+3)0.84% ami %268 (+3)1.09%

Experimental Results (cont) Ami49-2 (after soft-adjustment) 49 blocks, 12 buses Buses {0, 5, 9, 12, 18} {1, 10, 21, 25} {2, 28, 33} {3, 19, 22, 26, 29, 34} {4, 23, 27} {5, 35, 30, 6} {32, 31, 17} {11, 14, 15, 32, 33} {12, 8, 14} {44, 43, 7} {0, 3} {2, 47}

Experimental Results (cont) (b) Industry designs Filecad1cad2 Blocks4057 Buses1316 Time (s) Deadspace4.40%5.16% cad2 BDF Solution

Experimental Results (cont) (c) Bus grid test files Filegrid4grid5grid6grid7 Blocks Buses Time (s) Deadspace0% Optimal BDF Solution for grid7

Conclusion Analyze the relationship between bus ordering and sequence pair representation Propose an algorithm for simultaneous floorplanning and bus planning using simulated annealing Experimental results demonstrate its effectiveness and efficiency