11 Wireless Sensor Networks (WSN) CPU Group Preliminary Presentation Almir Davis Yong Zhang Halligan Hall 02/10/2005

22 Agenda  Project Description  Resources  CPU Group Goals  Task Schedule  Questions

33 Project Description The project’s objective is to design a network of independent sensors that would be able to sense the chemical structure of air’s particles and communicate the findings to the base computing station.

44 Mission Statement Our mission is to achieve a long life wireless sensor network in which each sensor unit will be independently controlled and operated by an on- board CPU.

55 WSN Block Diagram

66 Sensor Card

77 WSN Major Constraints and Parameters (1)  Power issues –Low power requirement forces CPU design to introduce duty cycles for the transceiver (sleep mode) –CPU will have to process sensor information locally and communicate it to the transceiver only if there is an interesting event –CPU might want to use scheduling of packets in order to send them to transceiver efficiently (only at certain instances of time) as well as to use scheduling to avoid wireless packet contention and congestion –CPU might want to accumulate a number of packets before sending them back-to-back to transceiver –CPU might want to compress data going wireless –CPU can turn off transceiver after receiving only a portion of unimportant packet

88 WSN Major Constraints and Parameters (2)  Communication issues –Transceiver might miss to receive a packet from the WSN if it is currently in sleep mode (design must account for such case) –Transceiver’s outgoing packet might collide with an incoming packet –TIO protocol might start malfunctioning but it must recover on its own as the network might not be able to reset itself easily –Special care must be taken in designing TIO protocol in respect to power (smaller bus widths, compressed data, maybe even piggybacked control-data bus)

99 Project Resources  Project Lead (Prof. Hwa Chang)  Transceiver design (Prof. Sameer Sonkusale)  Network design (Na Wang)  CPU design (Almir Davis)  System level research (Yong Zhang)

10 CPU Group Goals  Define CPU functionalities  Define SIO (Sensor IO protocol)  Define TIO (Transceiver IO protocol)  Specify CPU architecture  Design CPU  Verify CPU

11 Design Task Schedule (1) 1. Research various sensor designs and protocols it uses to communicate with the rest of the system 2. Research various transceiver designs and the protocols it uses to communicate with the rest of the system 3. Design SIO and TIO 4. Receive the approval for protocols from all parties involved 5. Research various transceiver functionalities as well as WSN protocol features 6. Come up with the set of features (functionalities) for the CPU 7. Architect the CPU 8. Write the CPU specification 9. Receive the approval of all parties involved 10. Design CPU –Design will be done using Cadence Verilog HDL and Debussy Wave Viewer –Technology will be selected once all the essential information about the system are collected and digested (CPLA technology most likely to be used) –Sythesis tool will be Amplify from Synplicity

12 Verification Task Schedule (2) 1. Synthesize the CPU design and test the speed 2. Verify functionalities using “CPU only” verification environment 3. Create a larger system environment involving the entire Sensor Card 4. Test the CPU using system environment  System environment will be built out of all on-board components (sensor, CPU, and transceiver)  The environment is planned to be in Verilog HDL  Components currently in design process will be substituted by BFMs (Bus Functional Models)  System environment should accurately simulate all the board’s component activities

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