Presenter: Jyun-Yan Li Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors Antonis Paschalis Department of Informatics & Telecommunications University of Athens, Greece Dimitris Gizopoulos Department of Informatics University of Piraeus, Greece Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’04) Citing count: 12

Software-based self-test (SBST) strategies are particularly useful for periodic testing of deeply embedded processors in low cost embedded systems that do not require immediate detection of errors and cannot afford the well-known hardware, software, or time redundancy mechanisms. In this paper, first, we identify the stringent characteristics of an SBST test program to be suitable for on-line periodic testing. Then, we introduce a new SBST methodology with a new classification scheme for processor components. 2

After that, we analyze the self-test routine code styles for the three more effective test pattern generation (TPG) strategies in order to select the most effective self-test routine for on-line periodic testing of a component under test. Finally, we demonstrate the effectiveness of the proposed SBST methodology for on-line periodic testing by presenting experimental results for a RISC pipeline processor. 3

On-line test divides into concurrent and non-concurrent  Concurrent utilizes hardware redundancy techniques 。 Large increase silicon area  Non-concurrent is useful for periodic testing Usually use hardware-based self-test (HBST) for on-line periodic testing  Decrease performance, hardware overhead and increase power consumption for embedded processor Using software-based self-test (SBST)  Generates high fault coverage test program 。 Small memory footprint, small execution time and low power consumption 4

5 SBST functional structural randomized [5-7] randomized [5-7] Regular deterministic TPG [9-10] Regular deterministic TPG [9-10] Test the critical components, like arithmetic & logic, register files Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors This paper: Targeting processor components [8-10] Targeting processor components [8-10] MIPS Plasma [13] MIPS Plasma [13] 3 stage pipeline with forwarding RISC processor high abstraction level as Instruction Set Architecture targeting processor Components as RTL descriptions High fault coverage, but large number of instruction Divide and conquer

Test program execution time < a quantum time cycle  If > quantum time, context switch overheads Without unresolved data hazards  Reduce pipeline stall cycles Temporal locality for loop, spatial locality for sequentially executed instruction  Reduce memory stall cycles Small data structured in arrays  Reduce memory stall cycles 6

Information extraction  Identify the component’s inputs and outputs 。 Multiplexers Near input and out  Identify instruction that carry out specific operation  Identify appropriate instruction(s) to control them 7 Information Extraction Component Classification & Test Priority (visible, partially, hidden) Self-Test Routine Development (selection among 3 TPG strategies) Phase A Phase B Phase C

Visible components (VC)  Data VC (D-VC) 。 ALU, shifter, register file, data field of pipeline register  Address VC (A-VC) 。 Instruction fetch unit, memory address register  Mixed (address-data) VC (M-VC) 。 PC-relative addressing Partially visible components (PVC)  Generate control signal as Processor Control Unit 。 implemented as FSM Hidden components (HC)  Increase performance 。 Forwarding unit, hazard detection unit 8

9 Data visible components (D-VC) Partially visible components (PVC) Address visible components (A-VC) Mixed visible components (M-VC) Test priority Input: (1) immediate (2) register (3) data memory Output: (1) register file (2) data memory (3) data register Affect the operation of visible components A lot of memory reference & cache miss overhead

Combinational D-VC, Low gate-level 2 ways:  Immediate addressing  In the memory and loop-based routine fetch 10 Under test instruction Store final result to memory Immediate addressing Loop-based

Combinational D-VC, low gate-level Loop-based software LFSR self-test routine 11 Implement software LFSR Under test instruction Store final result to memory

Combinational or sequential D-VC, High-level 2 ways:  Immediate addressing  In the memory and loop-based routine fetch 12 Under test instruction Store final result to memory

Deterministic ATPG based (immediate) Deterministic ATPG based (loop) Psedorandom based Regular deterministic based application Combinational D-VC Combinational D-VC with irregular structure Combinational or Sequential D-VC strategyLow gate-level High level Execution time SmallLargeLarge(*) Miss rateHigh I$ Low I$ High D$ Low I$ feature Number of test patterns is small acceptable fault coverage High fault coverage 13 (*): no describing in the paper

32 bits, 3 stage pipeline with forwarding MIPS processor  gates by 0.35um  Cache miss rate = 5%, miss penalty = 20 clock cycle  quantum time cycle = for testing memory controller 7 for unloaded to data memory

3 SBST strategy for on-line periodic testing  Deterministic ATPG based  Psedorandom based  Regular deterministic based To improve reliability of embedded system My comment  Aim processor component 。 The programmer have to know the most critical component  How to compact test responses 15