AIDA FEE64 development report August 2010 Progress after Texas CAD work Manufacturing 25th August 20101

Progress after Texas 1.Power supply re-think – Linear or Switch mode. Deferred until the internal power supply structure is redesigned. 2.Readout of ASICS sequence of handshake to stop the slip of data relative to the channel number. Deferred until after the new card manufacture has started. 3.Change the test input system and investigate the problems with saturated inputs feeding back into the test network. No work done on this area. 4.Why does location 0 in the internal peripheral get cleared at power-up. Deferred until after the new card manufacture has started. 5.FADC triggering – more complex options perhaps using a chipscope ILA as the source. Not yet required. 6.HEC + delayed pulser – why are there 2+ peaks from the pulser in the LEC range. Why do they go if the delay is >10mS. No work done on this area. 7.Design the earthing structure into the mechanics. Waiting for the new power supply structure design. Review of the existing grounding structure will be carried out as part of the pcb design. 8.Investigate and propose solutions for the apparent effect of different routing of the buffered preamp outputs having different noise performance. Perhaps change the relative position of the buffers and ADCs. This has been investigated. See the later narrative in this document. 25th August 20102

Progress after Texas 9.Why does the FADC signal range not cover the full ASIC output swing. This has been investigated and a solution is now being implemented. 10.Why does the discriminator readout system stop working at high rates. Deferred until after the new card manufacture has started. 11.What is the true maximum specified input rate for the system. Deferred until after the new card manufacture has started. 12.Send the broken TTi power supply back for repair. Completed – Refund in received. 13.Re-try the water cooling. Also with two modules in place and powered up. Deferred until the internal power supply structure is redesigned. 14.Try out the effect of an isolating transformer as a method of noise reduction in conjunction with Linear and Switch mode supplies. Deferred until the internal power supply structure is redesigned. 25th August 20103

Progress after Texas Problems with synchronising the FADC acquisition clocks No solution is yet found. A new version of the clock cleaning and distribution chip is available with a “0 – delay” option which implies the input and output clocks can be phase locked. This should lead to the ability to align the clocks by using software and FPGA resources. 25th August 20104

Progress after Texas Investigations of the effects of the DC-DC convertors on the multiplex readout. Four of the convertors have been disabled and connected to external linear supplies. The performance of the ASIC multiplex readout has improved. 25th August 20105

Progress after Texas The power supply system redesign. 25th August 20106

Progress after Texas Investigation of the code spread and noise in the FADCs. Detector Development Group, DDG, have been investigating the problems with the buffers that interface to the FADCs. The effect of changes to the buffering are shown as FFTs in a plot of all channels with colour to show relative signal intensity. 25th August 20107

Starting point 25th August 20108

Remove all 10pF capacitors 25th August 20109

Buffer Changes ADC6, ADA4932, R=444R ADC4: R=330R Vref buf removed and output shorted to ground. 25th August

CAD work The update of the schematic and the pcb to Revision A. Redesign: The remaining design work involves the clock distribution system as discussed earlier. The JTAG (FPGA programming) and the console connectors have been amalgamated to one connector which is designed to allow the connections to be made when the module is fully assembled using a small adaptor board with the standard connectors on. Work to simulate the FADC buffers to remove the problems of the feedback capacitor, oscillation and use of only part of the full scale of the FADC has been completed by I.Lazarus. The ASIC multiplex readout system has been simulated and redesigned to increase the conversion rate to 1Mhz and use the full range of the ADC by I.Lazarus. 25th August

CAD Work Schematic: Changes to the schematic are 60% complete in terms of the document detailing the changes to be done. The major changes to the 64 channels of buffering for the FADCs have been completed. The new power supply design is complete. The changes to the ASIC multiplex readout developed to accommodate the full range of the ADC and to increase the conversion speed, and hence the ASIC clock rate, from 500Khz to 1Mhz are complete. 25th August

CAD Work PCB: The layout of the power supply has proceeded to the point where the two uModules and their associated components fit into the existing power supply area. Places for the new LDOs have been identified. The new FADC buffer circuits have been installed. The PCB has not yet been lengthened. 25th August