1 © 2004 Hill, from Falsafi, Hill, Hoe, Lipasti, Shen, Smith, Sohi, Vijaykumar, & Wood  Chapter 2: Instruction Sets CS/ECE/752 Vax & Emer/Clark Instructor: Prof. Mark D. Hill Slides developed by Profs. Falsafi, Hill, Hoe, Lipasti, Shen, Smith, Sohi, Vijaykumar & Wood of Carnegie Mellon University, Purdue University, & University of Wisconsin CS/ECE/752 Vax & Emer/Clark Instructor: Prof. Mark D. Hill Slides developed by Profs. Falsafi, Hill, Hoe, Lipasti, Shen, Smith, Sohi, Vijaykumar & Wood of Carnegie Mellon University, Purdue University, & University of Wisconsin Computer Sciences Department Electrical & Computer Engineering Department University of Wisconsin-Madison

2 © 2004 Hill, from Falsafi, Hill, Hoe, Lipasti, Shen, Smith, Sohi, Vijaykumar, & Wood  Chapter 2: Instruction Sets VAX DEC 1977 VAX 11/780  upward compatible from PDP-11  32-bit words and addresses  virtual memory  16 GPRs (R15 PC, R14 SP), CCs  extremely orthogonal and memory-memory  decode as byte stream, variable in length (1-61 bytes)  opcode, operation, #operands, operand types

3 © 2004 Hill, from Falsafi, Hill, Hoe, Lipasti, Shen, Smith, Sohi, Vijaykumar, & Wood  Chapter 2: Instruction Sets VAX Data Types  8, 16, 32, 64, 128  char string, 8 bits/char  decimal, 4 bits/char  numeric string, 8 bits/digit

4 © 2004 Hill, from Falsafi, Hill, Hoe, Lipasti, Shen, Smith, Sohi, Vijaykumar, & Wood  Chapter 2: Instruction Sets VAX Addressing Modes  literal, 6 bits  8, 16, 32 bit immediates  register, register deferred  8, 16, 32 bit displacements  8, 16, 32 bit displacements deferred  indexed (scaled)  autoincrement, autodecrement  autoincrement deferred

5 © 2004 Hill, from Falsafi, Hill, Hoe, Lipasti, Shen, Smith, Sohi, Vijaykumar, & Wood  Chapter 2: Instruction Sets VAX Operations  data transfer including string move  arithmetic and logical (2 and 3 operands)  control (branch, jump, etc.)  e.g., AOBLEQ  function calls save state  bit manipulation  floating point: add, sub, mul, div, polyf  system: exception, VM  other: CRC, INSQUE

6 © 2004 Hill, from Falsafi, Hill, Hoe, Lipasti, Shen, Smith, Sohi, Vijaykumar, & Wood  Chapter 2: Instruction Sets VAX Example addl3 R1, 737(R2), #456  byte 1:addl3  byte 2:mode, R1  byte 3:mode, R2  byte 4-5:737  byte 6:mode  byte 7-10:456 VAX has too many modes and formats However, few modes/formats => fast decoding in the pipeline Argument for RISC?

7 © 2004 Hill, from Falsafi, Hill, Hoe, Lipasti, Shen, Smith, Sohi, Vijaykumar, & Wood  Chapter 2: Instruction Sets Emer and Clark’s VAX study Evaluation method: Microcode profiler 1 microPC

8 © 2004 Hill, from Falsafi, Hill, Hoe, Lipasti, Shen, Smith, Sohi, Vijaykumar, & Wood  Chapter 2: Instruction Sets Emer and Clark, cont. Opcode Frequencies  84% Simple opcodes  39% Change PC  17% Simple conditional branches  2.4% Procedure call/return  4.5% (fast) subroutine call/return PC Changing Instructions Type% Instr% Taken%All Taken Simple Loop Bit6433 Total How do these compare to RISC ISAs?

9 © 2004 Hill, from Falsafi, Hill, Hoe, Lipasti, Shen, Smith, Sohi, Vijaykumar, & Wood  Chapter 2: Instruction Sets Emer and Clark, cont. Operand Specifiers  1.3 specifiers per instruction  0.3 branch displacements per instruction Average instruction size = 3.8 bytes SpecifierFrequency Register41% Short literal16% Immediate 3% Base-displacement25% Register deferred 9% Total94% Scaled 6% RISC-like addressing modes