FPGA IMPLEMENTATION OF A GREEDY ALGORITHM FOR SET COVERING Set Covering Problem U= {u1,..., um} a finite set; S = {S1,...,Sn} a collection of subsets of.

Slides:



Advertisements
Similar presentations
Embedded Algorithm in Hardware: A Scalable Compact Genetic Algorithm Prabhas Chongstitvatana Chulalongkorn University.
Advertisements

Discrete Math for Computer Science. Mathematical Model Real-world Problem Computerized Solution Abstract Model Transformed Model picture of the real worldpicture.
Algorithms + L. Grewe.
Fig.2: Carry chain delay line: (a) logic block diagram; (b) Layout obtained using a Xilinx Virtex 5 FPGA; (c) simplified block diagram of the Virtex 5.
Max-Min D-Cluster Formation in Wireless Ad Hoc Networks - Alan Amis, Ravi Prakash, Thai Vuong, Dung Huynh Presenter: Nirav Shah.
Randomized k-Coverage Algorithms for Dense Sensor Networks
Mohamed Hefeeda 1 School of Computing Science Simon Fraser University, Canada Multimedia Streaming in Dynamic Peer-to-Peer Systems and Mobile Wireless.
Introduction CS 524 – High-Performance Computing.
1 Multicast Routing with Minimum Energy Cost in Ad hoc Wireless Networks Xiaohua Jia, Deying Li and Frankie Hung Dept of Computer Science, City Univ of.
1 Performed By: Khaskin Luba Einhorn Raziel Einhorn Raziel Instructor: Rivkin Ina Spring 2004 Spring 2004 Virtex II-Pro Dynamical Test Application Part.
UMass Lowell Computer Science Analysis of Algorithms Prof. Karen Daniels Fall, 2001 Lecture 1 (Part 3) Tuesday, 9/4/01 Greedy Algorithms.
CPSC 689: Discrete Algorithms for Mobile and Wireless Systems Spring 2009 Prof. Jennifer Welch.
3 -1 Chapter 3 The Greedy Method 3 -2 The greedy method Suppose that a problem can be solved by a sequence of decisions. The greedy method has that each.
Implicit Hitting Set Problems Richard M. Karp Harvard University August 29, 2011.
1 Software Testing and Quality Assurance Lecture 37 – Software Quality Assurance.
Define Embedded Systems Small (?) Application Specific Computer Systems.
V The DARPA Dynamic Programming Benchmark on a Reconfigurable Computer Justification High performance computing benchmarking Compare and improve the performance.
The Effect of Data-Reuse Transformations on Multimedia Applications for Different Processing Platforms N. Vassiliadis, A. Chormoviti, N. Kavvadias, S.
UMass Lowell Computer Science Analysis of Algorithms Prof. Karen Daniels Spring, 2002 Lecture 1 (Part 3) Tuesday, 1/29/02 Design Patterns for Optimization.
Implementation of DSP Algorithm on SoC. Characterization presentation Student : Einat Tevel Supervisor : Isaschar Walter Accompany engineer : Emilia Burlak.
1 DSP Implementation on FPGA Ahmed Elhossini ENGG*6090 : Reconfigurable Computing Systems Winter 2006.
EKT303/4 PRINCIPLES OF PRINCIPLES OF COMPUTER ARCHITECTURE (PoCA)
1 Miodrag Bolic ARCHITECTURES FOR EFFICIENT IMPLEMENTATION OF PARTICLE FILTERS Department of Electrical and Computer Engineering Stony Brook University.
© The McGraw-Hill Companies, Inc., Chapter 3 The Greedy Method.
Trigger design engineering tools. Data flow analysis Data flow analysis through the entire Trigger Processor allow us to refine the optimal architecture.
November , 2009SERVICE COMPUTATION 2009 Analysis of Energy Efficiency in Clouds H. AbdelSalamK. Maly R. MukkamalaM. Zubair Department.
High Performance, Pipelined, FPGA-Based Genetic Algorithm Machine A Review Grayden Smith Ganga Floora 1.
DATA MINING LECTURE 13 Absorbing Random walks Coverage.
A Cluster-Based Backbone infrastructure for broadcasting in MANETs Student: Pei-Yue Kuo
Optimal Selection of ATE Frequencies for Test Time Reduction Using Aperiodic Clock Sindhu Gunasekar Vishwani D. Agrawal.
SHA-3 Candidate Evaluation 1. FPGA Benchmarking - Phase Round-2 SHA-3 Candidates implemented by 33 graduate students following the same design.
VHDL Project Specification Naser Mohammadzadeh. Schedule  due date: Tir 18 th 2.
Approximation Algorithms
Major objective of this course is: Design and analysis of modern algorithms Different variants Accuracy Efficiency Comparing efficiencies Motivation thinking.
Problem Solving Techniques. Compiler n Is a computer program whose purpose is to take a description of a desired program coded in a programming language.
Fig.2: Carry chain delay line: (a) logic block diagram; (b) layout obtained; (c) simplified block diagram of the Virtex 5 slice. Principle of operations.
Mobile Agent Migration Problem Yingyue Xu. Energy efficiency requirement of sensor networks Mobile agent computing paradigm Data fusion, distributed processing.
Another story on Multi-commodity Flows and its “dual” Network Monitoring Rohit Khandekar IBM Watson Joint work with Baruch Awerbuch JHU TexPoint fonts.
EKT303/4 PRINCIPLES OF PRINCIPLES OF COMPUTER ARCHITECTURE (PoCA)
Hardware Accelerator for Combinatorial Optimization Fujian Li Advisor: Dr. Areibi.
Computer Science 101 Theory of Computing. Computer Science is... The study of algorithms, with respect to –their formal properties –their linguistic realizations.
A GRID solution for Gravitational Waves Signal Analysis from Coalescing Binaries: preliminary algorithms and tests F. Acernese 1,2, F. Barone 2,3, R. De.
Survey of multicore architectures Marko Bertogna Scuola Superiore S.Anna, ReTiS Lab, Pisa, Italy.
Practical Message-passing Framework for Large-scale Combinatorial Optimization Inho Cho, Soya Park, Sejun Park, Dongsu Han, and Jinwoo Shin KAIST 2015.
Design and Analysis of Algorithms (09 Credits / 5 hours per week) Sixth Semester: Computer Science & Engineering M.B.Chandak
Custom Computing Machines for the Set Covering Problem Paper Written By: Christian Plessl and Marco Platzner Swiss Federal Institute of Technology, 2002.
Young CS 331 D&A of Algo. NP-Completeness1 NP-Completeness Reference: Computers and Intractability: A Guide to the Theory of NP-Completeness by Garey and.
CMPSC 16 Problem Solving with Computers I Spring 2014 Instructor: Tevfik Bultan Lecture 4: Introduction to C: Control Flow.
ECE 448 Lecture 6 Finite State Machines State Diagrams vs. Algorithmic State Machine (ASM) Charts.
Onlinedeeneislam.blogspot.com1 Design and Analysis of Algorithms Slide # 1 Download From
HIGH LEVEL SYNTHESIS WITH AREA CONSTRAINTS FOR FPGA DESIGNS: AN EVOLUTIONARY APPROACH Tesi di Laurea di: Christian Pilato Matr.n Relatore: Prof.
Efficient Point Coverage in Wireless Sensor Networks Jie Wang and Ning Zhong Department of Computer Science University of Massachusetts Journal of Combinatorial.
Introduction to Multiple-multicast Routing Chu-Fu Wang.
Introductory Lecture. What is Discrete Mathematics? Discrete mathematics is the part of mathematics devoted to the study of discrete (as opposed to continuous)
PREPARED BY: Qurat Ul Ain SUBMITTED TO: Ma’am Samreen.
George Mason University Finite State Machines Refresher ECE 545 Lecture 11.
Prof. Yu-Chee Tseng Department of Computer Science
Topics Modeling with hardware description languages (HDLs).
Analytics and OR DP- summary.
ECE 448 Lecture 6 Finite State Machines State Diagrams vs. Algorithmic State Machine (ASM) Charts.
A Review of Processor Design Flow
Topics Modeling with hardware description languages (HDLs).
Lesson 15: Processing Arrays
Subset of Slides from Lei Li, HongRui Liu, Roberto Lu
NP-Completeness Reference: Computers and Intractability: A Guide to the Theory of NP-Completeness by Garey and Johnson, W.H. Freeman and Company, 1979.
H a r d w a r e M o d e l i n g O v e r v i e w
ICS 252 Introduction to Computer Design
ECE 448 Lecture 6 Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL code ECE 448 – FPGA and ASIC Design.
On Constructing k-Connected k-Dominating Set in Wireless Networks
Survey on Coverage Problems in Wireless Sensor Networks - 2
Presentation transcript:

FPGA IMPLEMENTATION OF A GREEDY ALGORITHM FOR SET COVERING Set Covering Problem U= {u1,..., um} a finite set; S = {S1,...,Sn} a collection of subsets of U such that USi= U. S* = {Si1,..., Sik}, S*  S, be a cover of U, that is USik = U. Problem: to select S* such that |S*| is minimum. Hardware Implementation  The RTGreedy algorithm has been specifically optimized to solve the Set-Cover problem in real-time applications.  It makes only use of bit-wise logic operators and simple finite-state machines and it is suitable to run on platforms with minimal computational resources, like embedded microprocessor or custom logic.  In order to test the achievable performance, we have designed a straightforward hardware implementation based on a Virtex-II XC2V2000 Xilinx FPGA.  The logic has been described with synthesizable VHDL language.  The code is parametric and it allows us to implement the algorithm for different data-set size. Benchmarks  We have simulated and tested three cases with (S=8, D=8), (S=16, D=16), (S=32, D=32) to study how the logic occupancy and the maximum clock frequency scale with the input data size.  The 32x32 implementation is discussed in details, with a description of the main logic blocks and the related timing.  We have run on it benchmarks with different probability density to profile the algorithm execution time versus the data- set complexity. References M.R. Garey, and D.S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, New York, NY: W.H.Freeman,, D.S. Johnson, “Approximation Algorithms for Combinatorial Problems”, Journal of Computer and System Sciences, 1974, pp S. Rampone, “Probability-driven Greedy Algorithms for Set Cover”, in Proc. VIII SIGEF Congress “New Logics for the New Economy", Naples, Italy, September, S. Dhar, M.Q. Rieck, S. Pai, and E.J. Kim, “Various Distributed Shortest Path Routing Strategies for Wireless Ad Hoc Networks”, in Proc. 5th Int. Work. on DistributedComputing – Lecture Notes in Computer Science, 2918, Springer Verlag, S. Dhar, M.Q. Rieck, S. Pai and E.J. Kim, “Distributed Routing Schemes for Ad Hoc Networks Using d-SPR Sets”, Journal of Microprocessors and Microsystems, Special Issue on Resource Management in Wireless and Ad Hoc Mobile Networks, vol. 28(8), 2004, pp S. Rampone, “An Efficient Greedy Approximation Methodology for Minimum Set Cover,” Journal of Discrete Algorithms, submitted for publication. Alberto Aloisio a,b, Paolo Branchni c, Vincenzo Izzo a,b, and Salvatore Rampone d a Università di Napoli “Federico II”, I Napoli, Italy b INFN – Napoli, Italy, I Napoli, Italy C INFN e Universita’ “Roma3”, Roma, Italy, d RCOST and DSGA – Università del Sannio, Via Port’Arsa 11, I Benevento, Italy CHEP06 Mumbai New greedy algorithms for approximating minimum set cover have been developed. The algorithms are based on a probability-driven greedy choice between subsets. The cost of probability distribution evaluation can still be unaffordable in real-time applications. We describe an implementation based on a FPGA which makes the algorithm suitable for embedded and real-time architectures. Probability driven greedy algorithm  choose the subset Si whose probability with respect to U is maximum,  delete the elements of Si from U, and  repeat this process until the ground set U is covered.