Slide 1 2. Verilog Elements

Slide 2 Why (V)HDL? (VHDL, Verilog etc.), Karen Parnell, Nick Mehta, “Programmable Logic Design Quick Start Handbook”, Xilinx Coorporation, June 2003, module Mult ( input [15:0] A, input [15:0] B, output [31:0] Y ); assign Y = A * B; endmodule

Slide 3 Advantages of HDL languages: –Easy to describe combinational circuits –High-level language – easy to be understand by both human and machine –Projects can be easily PARTITIONED and HIERARCHIZED – supports teamwork! –Allows for Design Reuse –Platform independent –Allows different levels of abstractization (what is this?) Abstractization: Hiding details of a project, insignifiant at a specific level. Abstractization level example Behaviour RTL Logic Layout Algorithmic level. Modelling systems and stimulus Machine-independent description: registers, logic, clocking “Gate-Level” netlist Physical level – technology dependent. For ex: 15um HDL – useful for the upper three levels

Slide 4 VERILOG – Generalities Verisign Logic (?) by Verisign. Inc. Historically: 1984 Gateway Design Automation Inc, bought then by Cadence Design Systems, inc. First IEEE standard in 1995: IEEE Std , then in 2001 – IEEE std , then in IEEE Standard Newest language extention: Verilog – AMS (Analog and Mixed Signal, standardized in 2008) What VHDL/Verilog is used for? –To describe DIGITAL Systems and Circuits –To describe a TESTBENCH (used to test those above…) –Verilog is NOT a Programming language !!! –A Programming Language represents: (incomplete definition?) A set of instructions and data, that is passed through a compiler or interpreter The compiler transforms the set of instructions into machine code The machine code is loaded into a MEMORY and executed by a PROCESSING UNIT –VHDL/Verilog do NOT comply with the above description!!! –Exception: A Testbench can be considered as a multi-threading program

Slide 5 VERILOG – Generalities For a (BEHAVIORAL) Simulator: –VHDL/Verilog for Digital Circuits: The Instructions (Statements) are EXECUTED in order to SIMULATE the functionality of the circuit –Testbenches are also EXECUTED to create the input signaling and output verification For a Synthesizer: –VHDL/Verilog for Digital Circuits: The statements are TRANSFORMED into digital elements (Logic gates, registers etc) –Testbenches are, by default, IGNORED by synthesizers Therefore we speak about two types of HDL code: VHDL/Verilog for Synthesis VHDL/Verilog for Tetbenches

Slide 6 2.a. VHDL/Verilog for Synthesis

Slide 7 VHDL/Verilog for Synthesis Generalities: EVERY DIGITAL CIRCUIT –Contains AT LEAST one input signal (port) (*), (**) –Contains AT LEAST one output signal (port) (**) –It may contain internal signals and lower-level components –(*) Assume the circuit contains an internal signal generator, the input can missing. NOT the case of FPGA designs! FPGA devices NEED EXTERNAL CLOCKING –(**) Circuits with no input and circuits with no output will be removed by the synthesizer in the optimization process. –(**) Same if the input ports are not read, or the output port is never written or constant

Slide 8 VHDL/Verilog for Synthesis Moreover: EVERY: –Port –Internal Signal –Internal Component –… is IDENTIFIED by a Name (IDENTIFIER) (*) –(*) The OR gate will be probably described as: assign Cout = C1 | C0; The synthesizer will generate an OR gate. Will the OR gate have no name? –Names i.e. IDENTIFIERS ARE IMPORTANT!

Slide 9 Verilog Syntax elements CASE SENSITIVE, keywords always written with small letters Comment: // until the end of line /* …Can extend on more than one line */ A statement (instruction) can extend to more than one line! More than one statements can be on the same line!!! Instruction delimiter: ; (Every instruction ends up with; ) Compound instructions: begin – end: neither begin, nor end are ended with ; Same for statements delimiting “the end of something”: endcase, endmodule etc.

Slide 10 Verilog Syntax elements List Delimiter :, The last element of a list does not have to be delimited! A list is not ended with, ! In a VHDL/Verilog code we assign signal and/or variable values. Verilog: Two type of assignments: Blocking: ‘=‘ Non-Blocking: for signals: ‘<=‘, for variables: ‘:=‘ Recommendation: In “always” statements use NON- BLOCKING assignments Inside of an “always” statements cannot mix non-blocking and blocking assignments So: use <= for assingmnets

Slide 11 Verilog Syntax elements How to give a numerical value to a signal? number_of_bits’[s]number_basevalue Exemple: 1’b0; 2’b10, 16’hffef, 8’ds123; Default numbering base: Decimal What is 0, or 1, or 121? i.e. represented on how many bits? s – signed value i.e. two’s complement Some synthesizers do not support signed value How to treat then a signed value?

Slide 12 Verilog Syntax elements USER IDENTIFIERS Can contain letters, numbers, underscore ‘_’, CANNOT contain special characters such as /, ‘, “ MUST start with letters Examples: Mysignal23-- correct rdy, RDY, Rdy-- these are DIFFERENT identifiers vector_/_vector-- NO: Special character, not allowed last line-- Spaces are not allowed next__state -- Two consecutive underscores are NOT allowed 10th_signal-- NO: Starts with a number open, reg -- NO: Are Verilog Keywords

Slide 13 Extended Identifiers: The Escape character \ allows for extended identifiers - Verilog ’93 +! \12name – can begin with a number: ALLOWED \last line\ -- ALLOWED \next__state\ -- ALLOWED \open\, \reg\ -- ALLOWED XST: may need extra synthesis options to support Verilog ‘93! Suggestion: try to avoid extended identifiers Verilog Syntax elements

Slide 14 Example for Naming convention (Xilinx) -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- parameters: "C_*" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_cmb" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase Verilog Syntax elements

Slide 15 To create a digital component, we start with…? The component’s interface signals Defined in MODULE Module contains the WHOLE code of the component, including the definitions for Ports – input, output and inout signals Parameters – can be overwritten from the upper hierarchical level Verilog Syntax elements

Slide 16 General Form Definition Naming Conventions - MUST be there [name] - Optional (does not have to be present) - Either name1 or name 2 [name1 | name2] – Optional name1 or name2 Example: port definition: [type] [size] ; OR: [wire | reg] [size] ;

Slide 17 Symbol Drawing Elements My_module A[7:0] B[7:0] CLK DATA[7:0] CE Input and Output Ports: Arrowheads will be usually missing Usually, inputs are at the left side, outputs at the right side. If not, arrows indicating direction should be present Inout ports: arrowheads should be present Arrowhead indicating that is a clock signal (convention!) These are only helpers, indicating the signal width. Recommended to be present

Slide 18 Symbol Drawing Elements My_module A[7:0] B[7:0] CLK DATA[7:0] CE Bus label designators are not part of the signal name!!! Do not write input A[7:0]! Syntactically is correct, but it will create an array of 8 signals, each signal of one bit wide Do not use arrays for input/output ports! The signal name is A The bus designator is [7:0] Correct form: input [7:0] A

Slide 19 Verilog Module Definition General Form Prior Verilog 2001: module [#(paramater_list)] ( ); //for each port in the list: [size] name; Example: My_module module My_module (A, B, CLK, DATA, CE); input [7:0] A; input [7:0] B; input CLK; inout [7:0] DATA; output CE; … endmodule My_module A[7:0] B[7:0] CLK DATA[7:0] CE This is a LIST of ports, end each element with, except the last one This is NOT a list of ports but port declaration statements, end each statement with ;

Slide 20 Verilog Module Definition General Form Newer form – more compact module [#(parameter_list)] ( ); Example: My_module module My_module (input [7:0] A, input [7:0] B, input CLK, inout [7:0] DATA, output CE); … endmodule My_module A[7:0] B[7:0] CLK DATA[7:0] CE This is a LIST of ports, end each element with, except the last one

Slide 21 Port directions input – Signal values can be ONLY READ, not written output – Signal values can be both read and written (assigned), with the restriction: A SIGNAL CAN BE ASSIGNED IN ONLY ONE PLACE, i.e. One assign statement (if the signal is wire type), or One always statement (if the signal is reg type) inout - Bidirectional signal (tri-state) - Although newer FPGA devices can have tristate buffers on-chip, it is recommended to be used only for connections outside the chip - Recommendations: - Use two different signals for reading and assigning input values - Use a separate control signal to control the direction of the inout signal

Slide 22 VHDL ENTITY Definition General Form entity is generic ( : := ;... ); port ( : ; …); end [entity] ; Example: My_module entity My_module is port (A: in std_logic_vector (7 downto 0); B: in std_logic_vector (7 downto 0); CLK: in std_logic; DATA: inout std_logic_vector (7 downto 0); CE: out std_logic ); end My_module; My_module A[7:0] B[7:0] CLK DATA[7:0] CE This is a LIST of port statements, end each element with ; except the last one VHDL: out ports can be written in only one place, but CAN NOT BE READ! An internal signal has to be declared and used to read the output port

Slide 23 Signal and port modes wire – Can be assigned only in a concurrent statement (assign) – Cannot have initial value! Example: wire s = 0; … assign s = … //NOT ALLOWED! s is already constant (0) Otherwise, the synthesizer would be forced to create a circuit like: reg – Can be assigned only in a sequential statement (always) – Can have initial value Example: reg q = 0; //Allowed

Slide 24 Port directions linked to modes input – By default, considered as wire, cannot be assigned anyway output, inout – If their type is not specified, by default are considered as wire – If needed to assign output ports in always statements, specify reg in port declaration – Example: output reg [7:0] Dout, output reg CE,... From upper level hierarchy, output or inout ports are always seen as wire Recommended design practice: declare output ports as wire Use an internal signal with _reg suffix and assign the output port to it In this way, port declarations does not have to change, only internal code

Slide 25 Hierarchical Connections: What port directions can be connected? Case Study: Upper level to lower level or vice versa Input to input: ALLOWED Input to output or output to input: NOT ALLOWED Input is already driven from outside. Don’t try to drive it from inside! Output to output: ALLOWED The output has to be driven from inside Bidirectional: Only to Bidirectional Din B CLK 8 A Dout EN 8 Din C CLK 8 Data EN 8 Module2 Module1 Din CLK 8 A Data 8 EN Top_module

Slide 26 Hierarchical Connections: What port directions can be connected? Case Study: At the same level Input to input: Allowed, but the connecting signal has to be driven! i.e. also connected to a source (output) Input to output or output to input: ALLOWED Output to output: Not ALLOWED Do not try to drive a signal by two different circuits! Bidirectional: Only to Bidirectional Din B CLK 8 A Dout EN 8 Din C CLK 8 Data EN 8 Module2 Module1 Din CLK 8 A Data 8 EN Top_module

Slide 27 Hierarchical Connections: Code example SSG Decoder: module Ssg_decoder #( parameter CLK_FREQ = , parameter REFRESH_RATE = 1000 ) ( input CLK, input RESET, input [15:0] DIN, output [3:0] AN, output [6:0] SSG ); //We have to define the internal signals wire CE; wire [3:0] AN_Int; wire [1:0] mux_addr; wire [3:0] mux_data; CLK CE_div Freq_divider Din CLK 16 Ssg_decoder CLK CE Shift_reg_walk_0 RESET AN 4 Din Dout Priority_decoder 4 2 I0 4 I1 4 I2 4 I3 4 O 4 2 A Mux_4X_4To1 Din Dout Hex_to_ssg_encoder SSG AN 4 Din[3:0] [7:4] [11:8] [15:11] RESET CE AN_Int mux_data mux_addr CLK RESET Din 16 #(CLK_FREQ REFRESH_RATE) #(CLK_FREQ, DIV_RATE) Ssg_decoder #(CLK_FREQ, REFRESH_RATE) AN 4 7 SSG CE AN_Int mux_addr mux_data

Slide 28 Hierarchical Connections: Code example SSG Decoder: //connect now the internal modules //each module connection can be taken //from its definition: CLK CE_div Freq_divider Din CLK 16 Ssg_decoder CLK CE Shift_reg_walk_0 RESET AN 4 Din Dout Priority_decoder 4 2 I0 4 I1 4 I2 4 I3 4 O 4 2 A Mux_4X_4To1 Din Dout Hex_to_ssg_encoder SSG AN 4 Din[3:0] [7:4] [11:8] [15:11] RESET CE AN_Int mux_data mux_addr CLK RESET Din 16 #(CLK_FREQ REFRESH_RATE) #(CLK_FREQ, DIV_RATE) Ssg_decoder #(CLK_FREQ REFRESH_RATE) AN 4 7 SSG CE AN_Int mux_addr mux_data module #( parameter ) ( input output ); = , = Freq_divider CLK_FREQ DIV_RATE CLK, CE_div #( ) ( );

Slide 29 Hierarchical Connections: Code example SSG Decoder: //connect now the internal modules //each module connection can be taken //from its definition: CLK CE_div Freq_divider Din CLK 16 Ssg_decoder CLK CE Shift_reg_walk_0 RESET AN 4 Din Dout Priority_decoder 4 2 I0 4 I1 4 I2 4 I3 4 O 4 2 A Mux_4X_4To1 Din Dout Hex_to_ssg_encoder SSG AN 4 Din[3:0] [7:4] [11:8] [15:11] RESET CE AN_Int mux_data mux_addr CLK RESET Din 16 #(CLK_FREQ REFRESH_RATE) #(CLK_FREQ, DIV_RATE) Ssg_decoder #(CLK_FREQ REFRESH_RATE) AN 4 7 SSG CE AN_Int mux_addr mux_data Freq_divider #(. CLK_FREQ. DIV_RATE ) (. CLK. CE_div ); (CLK_FREQ), (REFRESH_RATE) My_Freq_divider_inst (CLK), (CE) #(CLK_FREQ, DIV_RATE) #(CLK_FREQ REFRESH_RATE) Remember: If the module has parameters to override, the instance name comes AFTER the parameter connections! Check for the commas in the parameter and port list!

Slide 30 Hierarchical Connections: Code example SSG Decoder: CLK CE_div Freq_divider Din CLK 16 Ssg_decoder CLK CE Shift_reg_walk_0 RESET AN 4 Din Dout Priority_decoder 4 2 I0 4 I1 4 I2 4 I3 4 O 4 2 A Mux_4X_4To1 Din Dout Hex_to_ssg_encoder SSG AN 4 Din[3:0] [7:4] [11:8] [15:11] RESET CE AN_Int mux_data mux_addr CLK RESET Din 16 #(CLK_FREQ REFRESH_RATE) #(CLK_FREQ, DIV_RATE) Ssg_decoder #(CLK_FREQ REFRESH_RATE) AN 4 7 SSG CE AN_Int mux_addr mux_data Freq_divider #(. CLK_FREQ (CLK_FREQ),. DIV_RATE (REFRESH_RATE) ) My_Freq_divider_inst (. CLK(CLK). CE_div (CE) ); //OR, keeping the order of parameters and //ports, the shortened version does not have //to contain the formal (internal) //parameters and ports: Freq_divider #(CLK_FREQ, REFRESH_RATE) My_Freq_divider_inst (CLK, CE); #(CLK_FREQ, DIV_RATE) #(CLK_FREQ REFRESH_RATE) //NOT RECOMMENDED FOR //LARGE COMPONENTS: REDUCES //CODE VISIBILITY DRASTICALLY

Slide 31 Hierarchical Connections: Code example SSG Decoder: //In a similar manner: Shift_reg_walk_0 My_shift_reg_inst (.CLK (CLK),.RESET (RESET),.CE (CE),.AN (AN_Int) ); Priority_decoder My_decoder (.Din (AN_Int),.Dout (mux_addr)); Mux_4X_To1 My_mux_inst (.I0 (Din[3:0]),.I1 (Din[7:4]),.I2 (Din[11:8]).I3 (Din[15:11]),.A (mux_data),.O (mux_addr) ); Hex_to_ssg_encoder My_encoder_inst (.Din (mux_data),.Dout (SSG) ); endmodule CLK CE_div Freq_divider Din CLK 16 Ssg_decoder CLK CE Shift_reg_walk_0 RESET AN 4 Din Dout Priority_decoder 4 2 I0 4 I1 4 I2 4 I3 4 O 4 2 A Mux_4X_4To1 Din Dout Hex_to_ssg_encoder SSG AN 4 Din[3:0] [7:4] [11:8] [15:11] RESET CE AN_Int mux_data mux_addr CLK RESET Din 16 #(CLK_FREQ REFRESH_RATE) #(CLK_FREQ, DIV_RATE) Ssg_decoder #(CLK_FREQ REFRESH_RATE) AN 4 7 SSG CE AN_Int mux_addr mux_data #(CLK_FREQ, DIV_RATE) #(CLK_FREQ REFRESH_RATE) There are at least two errors in the code! Where? SSG Decoder: //In a similar manner: Shift_reg_walk_0 My_shift_reg_inst (.CLK (CLK),.RESET (RESET),.CE (CE),.AN (AN_Int) ); Priority_decoder My_decoder (.Din (AN_Int),.Dout (mux_addr)); Mux_4X_To1 My_mux_inst (.I0 (Din[3:0]),.I1 (Din[7:4]),.I2 (Din[11:8]),.I3 (Din[15:11]),.A (mux_data),.O (mux_addr) ); Hex_to_ssg_encoder My_encoder_inst (.Din (mux_data),.Dout (SSG) ); endmodule

Slide 32 Hierarchical Connections: Code example SSG Decoder: //Corrected version: Shift_reg_walk_0 My_shift_reg_inst (.CLK (CLK),.RESET (RESET),.CE (CE),.AN (AN_Int) ); Priority_decoder My_decoder (.Din (AN_Int),.Dout (mux_addr)); Mux_4X_To1 My_mux_inst (.I0 (Din[3:0]),.I1 (Din[7:4]),.I2 (Din[11:8]),.I3 (Din[15:11]),.A (mux_addr),.O (mux_data) ); Hex_to_ssg_encoder My_encoder_inst (.Din (mux_data),.Dout (SSG) ); endmodule CLK CE_div Freq_divider Din CLK 16 Ssg_decoder CLK CE Shift_reg_walk_0 RESET AN 4 Din Dout Priority_decoder 4 2 I0 4 I1 4 I2 4 I3 4 O 4 2 A Mux_4X_4To1 Din Dout Hex_to_ssg_encoder SSG AN 4 Din[3:0] [7:4] [11:8] [15:11] RESET CE AN_Int mux_data mux_addr CLK RESET Din 16 #(CLK_FREQ REFRESH_RATE) #(CLK_FREQ, DIV_RATE) Ssg_decoder #(CLK_FREQ REFRESH_RATE) AN 4 7 SSG CE AN_Int mux_addr mux_data #(CLK_FREQ, DIV_RATE) #(CLK_FREQ REFRESH_RATE)

Slide 33 Hierarchical Connections Example in VHDL SSG Decoder: architecture my_arch of ssg_decoder is --internal signals signal CE: std_logic; signal AN_Int: std_logic_vector (3 downto 0); signal mux_addr: std_logic_vector (1 downto 0); signal mux_data: std_logic_vector (3 downto 0); --we have to declare each component --if not included in library component Freq_divider generic ( CLK_FREQ: integer := ; DIV_RATE : integer := 1000 ); port (CLK : in std_logic; CE_div: out std_logic ) end component; … begin For component declaration the semicolon is present Every signal and component declaration is done between the architecture… begin statements

Slide 34 Hierarchical Connections Example in VHDL SSG Decoder: … begin My_Freq_divider_inst: Freq_divider generic map ( CLK_FREQ => CLK_FREQ, DIV_RATE => REFRESH_RATE ) port map ( CLK => CLK, CE_div => CE ); -- other instantiations -- and statements … end architecture my_arch; Component instantiations and statements are done between the begin… end architecture statements For component instantiation the semicolon is not present Generic map and port map statements are followed by a list of ports, separated by commas

Slide 35 Verilog for synthesis: What operators can we use? Operators can be used in both assign and always statements Logical bitwise operators: &, |, ~, ^, ~^ Operation applies to each bit of a signal Therefore, apply operators to signals with the SAME WIDTH only Otherwise, the signal with lower width will be left aligned (some synthesizers might align it to right) Logical operators: !, &&, ||, ==, !=, ===,, =, !== Used in conditions only. Same as in C, a condition is written always in () What is === and !== ? Signals are compared including X and Z Note: X = don’t care, not undefined! Applies to simulation only!

Slide 36 Verilog for synthesis: What operators can we use? Operators can be used in both assign and always statements Arithmetic operators: +, -, *, /, %, ** /, % and ** can be synthesized only if the second operand is 2 or power of 2! Shift: >, >> Shifted in values are 0 >> : shift and maintain sign bit Unary reduction operators &, ~&, |, ~|, ~, ^, ~^, Concatenate and replicate { }, {{}}

Slide 37 Verilog for synthesis: What operators can we use? Unary reduction operators Example: We have a N-bit wide signal named A. The width of A is determined by a parameter called SIGNAL_WIDTH. We have to make a logic AND between all of the bits of A into a signal called A_and. How can we do this? Solution 1: … wire [SIGNAL_WIDTH-1:0] A; reg A_and; integer I; (A) for (i=0; i<SIGNAL_WIDTH; i = i+1) A_and <= A_and & A[i]; Solution 2: … wire A_and; assign A_and = &A; Note: To test whether any of the bits of A is 1, one can use (|A)

Slide 38 Verilog for synthesis: What operators can we use? Concatenate and replicate Concatenate Examples: 1. {a, b, c} – Concatenate a, b, c into a bus The width of the resulting bus = width of a + width of b + width of c Concatenate assignment is also positional! The leftmost bit of the resulting bus is the leftmost bit of a 2. Assume the following code snippet: wire [7:0] a; wire [2:0] b; wire [4:0] c; wire [18:0] q; assign q = {a[5:0], c[3:0], b, a[7:6], 1’b0, 2’b10, b[2]}; What will be connected to q[17], q[7] and q[2]?

Slide 39 Verilog for synthesis: What operators can we use? Concatenate and replicate Replicate Examples: 1.We have a N-bit wide signal called A and a 1-bit wide signal called EN. The value of N is determined by the parameter SIGNAL_WIDTH. The EN signal acts as an enable for the N-bit wide output signal A_out such as A_out = A if EN = 1, otherwise all of the bits of A are 0. How can we do this? Solution 1: assign A_out = (EN)? A:0; //works only if A is less than 32-bit wide! Otherwise: N’h00…. Solution 2: assign A_out = A & {SIGNAL_WIDTH{EN}}; 2. wire [19:0] q = {{2{4’hA}}, {4{3’b101}}}. Write down in hexadecimal the value of Q!

Slide 40 Verilog for synthesis: About indexes One-dimension signals i.e. BUSES: How to access a part of a bus? Example: wire | reg [N:n] A; N and n are POSITIVE INTEGER numbers A[Upper:Lower] always represents the CONTINUOUS part of the bus having the width of Upper-Lower+1 Assume Upper >= Lower, then ALWAYS Upper =n! Otherwise the Verilog parser generates an error. Careful when using parameters or variables for indexing! The synthesizer is able to determine if the index is out of the range [N:n]. Example: reg [15:0] A; … for (i=0; i<=16; i++) A[i] <= … //will generate an error For selecting non-continuous parts of A, use concatenation operators A[i] ALWAYS represents a 1-bit wide signal. Obviously, n<=i<=N A ALWAYS represents the WHOLE range of A, equivalent to A[N:n] Note: A[N:N] is valid if A was defined in this way! Example: parameter SIGNAL_WIDTH = 0; reg [SIGNAL_WIDTH-1:0] A; //A will be defined as A[0:0]

Slide 41 Verilog for synthesis: About indexes One-dimension signals i.e. BUSES: How to access a part of a bus? Example: wire | reg [N:n] A; What about accessing part of A as A[Lower:Upper]? Syntactically it is accepted but the synthesizer will generate an error Use the endianness of signals in the way they wer defined! RECCOMENDATION: use only one endianness in your code! (usually little) If cannot avoid both little and big endian signals, in your code, Example: wire [Lower:Upper] B = A [Upper:Lower];//B[Lower] = A[Upper]… Two-dimension signals i.e. ARRAYS Example: reg [N:n] A [m:M]; //It can be also [M:m] Used mostly for MEMORY structures: RAM, ROM, FIFO and multi- dimensional shift registers ALWAYS THE SECOND INDEX COMES FIRST! A[ i ], m<= i <=M ALWAYS represents a N-n+1-width signal i.e the i-th location of the memory or shift register

Slide 42 Verilog for synthesis: About indexes Two-dimension signals i.e. ARRAYS Example: reg [N:n] A [m:M]; //It can be also [M:m] A[ i ], m<=i<=M ALWAYS represents a N-n+1-width signal i.e the i-th location of the memory or shift register, equivalent to A [ i ] [N:n] A[ i ][ j ], m<= i <=M, n <= i <= N ALWAYS represents bit j of location i A[ i ][Upper:Lower] ALWAYS represents a part selector of the bus from location i A [L1:U1] [U2:L2] is syntactically valid, but the synthesizer will generate an error For example: reg [7:0] Mem [0:255]; … begin Mem <= 0; //NOT ALLOWED. Mem is an array of 256X8! Not 32 bits //and not even 2048 bits! Mem [0:3] <= {32{1’b0}}; //Also not allowed Mem [3] <= 8’hFF;//Allowed Mem [255] [7:4] <= 4’h8;//Allowed

Slide 43 Verilog for synthesis: About indexes Multi-Dimension signals? Example: reg [N:n] A [m:M] [p:P]; //It can be also [m:M], [P:p] and so on It will be visible as a three-dimensional memory ALWAYS, THE SECOND INDEX COMES FIRST! XST solves the three-dimensional array as a two-dimensional array of (P-p+1) * (N-n+1) X (M-m+1) The third index i.e. [p:P] represents a multiplier for the first index i.e. [N:n] Therefore A[ i ] [ j ], m<= i <=M, p <= j <= P represents a N-n+1-width signal i.e the i-th location, bits [ (( j+1 ) * N) + j : (( j+1 ) * N ) + j – (N-n) ] of the memory, or shift register, equivalent to A [ i ] [ j ] [N:n] A[ i ][ j ][ k ], m<= i <=M, p <= i <= P, n <= k <=N represents bit j*k of location i A[ i ][ j ][Upper:Lower] represents a part selector [ (j * Upper: j * Lower] of the bus from location i A [L1:U1] [U2:L2] is not accepted by the synthesizer, it will generate an error Example: reg [7:0] Mem [0:255][0:3]; //will generate an array of 256 X 32- bit wide registers

Slide 44 VHDL: About indexes One-dimension signals i.e. BUSES: Example: signal A: std_logic_vector (7 downto 0); signal B, C: std_logic_vector (0 to 3); Index can be also negative! Part selectors: Valid: A (5 downto 4); B(0 to 2); A (5 downto 5); C(0 to 3); Invalid, even syntactically is not accepted to change the endianness or using indexes larger than the range: A (3 to 7); B(3 downto 0); C(0 downto 0); A(8), A(6 downto -1); A is equivalent to A(7 downto 0), B to B(0 to 3) and so on 1-bit value: enclosed in ‘ ‘, multiple-bit values: enclosed in “ “ Hexadecimal prefix: X Concatenation operator: &. Examples: A <= C & B; -- A(7) <= C(0), A(6) <= C(1) and so on A <= ‘0’ & B &”000”; A<= X”FF”; B <= C(0 to 2) & ‘1’;

Slide 45 VHDL: About indexes Multi-dimension signals i.e. ARRAYS: First, the type of array has to be defined. Example: type my_mem2type is array (0 to 7) of std_logic_vector ( 15 downto 0); type my_mem3type is array (0 to 3) of my_mem2type; signal A: my_mem2type; signal B: my_mem3type; The first defined index comes first! Part selectors: similar to Verilog A(7); A(5) (5 downto 4); B(3) (7) (15); Invalid: A (3 to 7); B(2 to 3) etc.

Slide 46 Verilog for Synthesis: Behavioral description Instead of instantiating components, describe them using behavioral description in a single module Connect the various components using internal signals Advantages: Often allows for shorter description A single module may be needed to describe a project consisting of various components Easier to understand the behavior of the internal components Disadvantages: It might reduce code readability – Comments here are necesarry! Can lead to large files i.e. hundredths of lines of code

Slide 47 Verilog for Synthesis: Behavioral description example SSG Decoder again: module Ssg_decoder #( parameter CLK_FREQ = , parameter REFRESH_RATE = 1000) (input CLK, input RESET, input [15:0] DIN, output [3:0] AN, output [6:0] SSG); //now we need more internal signals //to make the frequency divider wire CE; integer Freq_divider; //to make the shift register reg [3:0] AN_Int; //to make the multiplexer wire [3:0] mux_data; //mux_addr disappeard! The priority //decoder will be also made using behavioral // description //to make the Hex_to_ssg_decoder reg [6:0] SSG_Int; CLK CE_div Freq_divider Din CLK 16 Ssg_decoder CLK CE Shift_reg_walk_0 RESET AN 4 Din Dout Priority_decoder 4 2 I0 4 I1 4 I2 4 I3 4 O 4 2 A Mux_4X_4To1 Din Dout Hex_to_ssg_encoder SSG AN 4 Din[3:0] [7:4] [11:8] [15:11] RESET CE AN_Int mux_data mux_addr CLK RESET Din 16 #(CLK_FREQ REFRESH_RATE) #(CLK_FREQ, DIV_RATE) Ssg_decoder #(CLK_FREQ REFRESH_RATE) AN 4 7 SSG CE AN_Int mux_addr mux_data #(CLK_FREQ, DIV_RATE) #(CLK_FREQ REFRESH_RATE)

Slide 48 SSG Decoder again: //describe the divider (posedge CLK) if (Freq_divider == ((CLK_FREQUENCY_HZ/REFRESH_RATE) - 1 )) Freq_divider <=0; else Freq_divider <= Freq_divider + 1; //assign the divided signal assign CE = (CE_div == ((CLK_FREQUENCY_HZ/REFRESH_RATE) - 1 )) ? 1:0; //note: CE is one-shot signal! //describe the walking 0 shift register (posedge CLK or posedge RESET) if (RESET) AN_Int<=4'hf; else if (CE) if (AN_Int==4'b0111 || AN_Int==4'b0000 || AN_Int==4'b1111) AN_Int<=4'b1110; else AN_Int <= {AN_Int[2:0],1'b1}; //shift register Verilog for Synthesis: Behavioral description example

Slide 49 SSG Decoder again: //Priority encoder and multiplexer combined assign mux_data = (An_Int==4'b1110) ? DIN[3:0] : (An_Int==4'b1101) ? DIN[7:4] : (An_Int==4'b1011) ? DIN[11:8] : (An_Int==4'b0111) ? DIN[15:12] : 4'h0; Verilog for Synthesis: Behavioral description example

Slide 50 SSG Decoder again: //write the seven segment decoder (mux_data) case (mux_data) 4'b0001: Ssg_Int=7'b ; //1 4'b0010: Ssg_Int=7'b ; //2 4'b0011: Ssg_Int=7'b ; //3 4'b0100: Ssg_Int=7'b ; //4 4'b0101: Ssg_Int=7'b ; //5 4'b0110: Ssg_Int=7'b ; //6 4'b0111: Ssg_Int=7'b ; //7 4'b1000: Ssg_Int=7'b ; //8 4'b1001: Ssg_Int=7'b ; //9 4'b1010: Ssg_Int=7'b ; //A 4'b1011: Ssg_Int=7'b ; //B 4'b1100: Ssg_Int=7'b ; //C 4'b1101: Ssg_Int=7'b ; //D 4'b1110: Ssg_Int=7'b ; //E 4'b1111: Ssg_Int=7'b ; //F default: Ssg_Int=7'b ; //0 endcase Verilog for Synthesis: Behavioral description example

Slide 51 SSG Decoder again: //Do NOT forget to assign the outputs! //Otherwise, the module will be REMOVED //by the synthesizer assign AN = AN_Int; assign SSG = SSG_Int; // Suggestion 1: better make the output //assignment at the beginning of the file! //Suggestion 2: for each component to be made, //write its comment first, then fill the code //with instructions! Such as: //Here comes the frequency divider //Here comes the shift register //… endmodule Verilog for Synthesis: Behavioral description example

Slide 52 SSG Decoder again: //Do NOT forget to assign the outputs! //Otherwise, the module will be REMOVED //by the synthesizer assign AN = AN_Int; assign SSG = SSG_Int; // Suggestion 1: better make the output //assignment at the beginning of the file! //Suggestion 2: for each component to be made, //write its comment first, then fill the code //with instructions! Such as: //Here comes the frequency divider //Here comes the shift register //… endmodule Verilog for Synthesis: Behavioral description example

Slide 53 Q: Which one should I use: Behavioral or Hierarchical description? A: It depends... Create modules that can be REUSED. Those later can be used as hierarchical components in other projects. Examples: Ssg_Decoder Your components in your project need to run at several different frequencies? Create a PARAMETRIZED divider then use it! You can describe the divider using behavioral description, NOT as a set of counters and comparators! Conclusion (?): Decide based on the experience you have I.e. try both There is a reason for the existence of project managers! Verilog for Synthesis: Behavioral description

Slide 54 Q: What signals should I declare: wire or reg? A: 1. For SEQUENTIAL components/signals (components running synchronous to a clock signal): The answer is clearly reg (the signal has to be assigned in a (posedge CLK) statement! 2.For COMBINATIONAL components/signals: Use continuous (assign) assignments whenever possible (also if it worth) You avoid in this way incomplete assignments (what are those…?) – the syntax checker will generate an error in the case of an incomplete assignment! Combinational loops (again, what are those…?) cannot be avoided To describe logic with many inputs and outputs such as state- machine logic or decoders/encoders, consider using always statements There is a risk of both incomplete assignments and combinational loops Verilog for Synthesis: Behavioral description

Slide 55 To describe logic with many inputs and outputs such as state-machine logic or decoders/encoders, consider using always statements Example: the Hex_to_ssg decoder, if it would be made using continuous assignments: assign Ssg_Int = (mux_data == 4’b0001) ? 7’b : (mux_data == 4’b0010) ? 7’b : …. More text/symbols to write than using a case statement: case (mux_data) 4'b0001: Ssg_Int=7'b ; //1 4'b0010: Ssg_Int=7'b ; //2 … default: Ssg_Int=7'b ; //0 endcase Special casez or casex statements in Verilog: casez: treat ‘z’ as don’t care, casex: treat ‘z’ and ‘x’ as don’t care Used mostly in simulation (testbenches) Verilog for Synthesis: Behavioral description

Slide 56 Example: (posedge CLK or posedge Reset or posedge Load) if (Reset) cnt <= 0; else if (Load) cnt <= Din; else if (CE) cnt <= cnt +1; CLK will be the CLOCK signal NOT BECAUSE IS CALLED CLK! Because is the signal that is not present as a CONDITION in the code! Remember that the clock signal is the one that gives the RHYTHM of a synchronous circuit! (as a cowbell for cows or drum for music) Also, Reset is the reset signal, Load is the load signal, Reset has HIGHER PRIORITY, BOTH ARE ACTIVE_HIGH and BOTH ARE ASYNCHRONOUS because: The (Reset) condition causes cnt <= 0. (Reset) is equivalent to (Reset == 1’b1) (Reset is a reset signal) The (Load) condition causes cnt <= Din (Load is a load signal) Reset is checked BEFORE Load! (Reset has higher priority) BOTH signals are in the sensitivity list as posedge, also checked against 1 (Both are asynchronous and active-high) … Not because the reset signal is called Reset and … Verilog for Synthesis: Sequential always statements

Slide 57 Example: (posedge CLK or posedge Reset or posedge Load) if (Reset) cnt <= 0; else if (Load) cnt <= Din; else if (CE) cnt <= cnt +1; CE is a Clock Enable signal and is SYNCHRONOUS Because enables counting Because CE DOES NOT APPEAR IN THE SENSITIVITY LIST The asynchronous signals have always HIGHER priority than the synchronous signals Then the asynchronous signals have to be tested FIRST! Example (BAD): (posedge CLK or posedge Reset or posedge Load) if (CE) cnt <= cnt +1; else if (Reset) cnt <= Din;.. Verilog for Synthesis: Sequential always statements

Slide 58 Example: (posedge CLK or posedge Reset or posedge Load) if (Reset) cnt <= 0; else if (Load) cnt <= Din; else if (CE) cnt <= cnt +1; The asynchronous signals have always HIGHER priority than the synchronous signals Then the asynchronous signals have to be tested FIRST! Example (BAD): (posedge CLK or posedge Reset or posedge Load) if (CE) cnt <= cnt +1; else if (Reset) cnt <= Din; Example (GOOD!) (posedge CLK or posedge Reset or posedge Load) begin if (CE) cnt <= cnt +1; if (Load) cnt <= Din; if (Reset) cnt <= 0; The last change (if the condition is true) is cnt <= 0;. Therefore Reset has the highest priority! Not recommended. Some synthesizers may not recognize the counter Verilog for Synthesis: Sequential always statements

Slide 59 Example: (posedge CLK or posedge Reset or posedge Load) if (Reset) cnt <= 0; else if (Load) cnt <= Din; else if (CE) cnt <= cnt +1; The posedge or negedge statements have to be in conjunction with the condition tested Otherwise the synthesizer generates an error Examples (BAD): (posedge CLK or posedge Reset or posedge Load) if (!Reset) cnt <= cnt +1; else if (Reset) cnt <= Din; … (posedge CLK or negedge Reset or posedge Load) if (CE) cnt <= cnt +1; else if (Reset) cnt <= Din; … Verilog for Synthesis: Sequential always statements

Slide 60 Avoid describing combinational logic for asynchronous control signals! Example (BAD): (posedge CLK or posedge Reset1 or posedge Reset2) if (Reset1 || Reset2) cnt <= 0; else if (Load) cnt <= Din; else if (CE) cnt <= cnt +1; ISE 12.2 may accept it, ISE 12.3 or 13.X might not! (calling XST in batch mode from EDK, for example) Reason: it may “believe” that we want to syntesize a sequential circuit with two reset signals! Example (correct) wire Reset = Reset1 | Reset2; (posedge CLK or posedge Reset) if (Reset) cnt <= 0; … Verilog for Synthesis: Sequential always statements

Slide 61 Avoid using the SAME priority for asynchronous and synchronous control signals! Example (BAD): (posedge CLK or posedge Reset1) if (Reset1 || Reset2 || Reset3) cnt <= 0; else if (Load) cnt <= Din; else if (CE) cnt <= cnt +1; Reset1 is asynchronous, but Reset2 and Reset3 are synchronous! Have you seen a flip-flop with both synchronous and asynchronous reset, also with synchronous load? It is possible to make it. How? Then describe the circuit so! Example (correct): Make all of the reset signals either synchronous or asynchronous wire Reset = Reset1 | Reset2 | Reset3; (posedge CLK or posedge Reset) if (Reset) cnt <= 0; … Or: wire Reset = Reset1 | Reset2 | Reset3; (posedge CLK) … Verilog for Synthesis: Sequential always statements

Slide 62 Generates COMBINATIONAL CIRCUITS Example: (A or B or C) if (A) D <= 1; else if (B||C) D <=1; else D <= 0; What circuit will be generated by the synthesizer? Note: for combinational always statements, both changes (from 0 to 1 or from 1 to 0 matter) – combinational circuits may change their output when the input changes, regardless of a clock signal Do not use posedge or negedge conditions for combinational always statements! It may either: Make a sequential circuit, if there is an extra signal in the sensitivity list, or Synthesizer generates an error Verilog for Synthesis: Combinational always statements

Slide 63 Generates COMBINATIONAL CIRCUITS All the signals read inside the always statements should be on the sensitivity list, otherwise simulation differences appear between behavioral and post-translate! Reason: The syntesizer IGNORES the sensitivity list and will connect signals read inside the always statement, only generates a warning The simulator WILL NOT run the always statement when a signal changes, if the signal is not on the sensitivity list! Conclusion: DO NOT make exclusions based on the sensitivity list! Verilog for Synthesis: Combinational always statements

Slide 64 Combinational always statements: include decision-based statements: if..else, case..endcase Every if has to have an else branch! Every case has to have every branch (default, if not) Otherwise: we have incomplete assignments that lead to latch inference! SO: What to avoid in combinational always statements? Verilog for Synthesis: Combinational always statements

Slide 65 Combinational always statements: To avoid (I.E. What to DO NOT in your Verilog code!) Synthesis Warnings

Slide 66 1.Make INCOMPLETE ASSIGNMENTS 2.Exclude based on the SENSITIVITY LIST 3.Make COMBINATIONAL LOOPS Why these are not treaten as an error by the synthesizer? DO NOT: Verilog for Synthesis: Combinational always statements

Slide INCOMPLETE ASSIGNEMNTS in combinational always statements Example module NOT_GOOD( input A, input B, input SEL, output reg Q); (A or B or SEL) if (SEL) Q<=A; endmodule WHAT WILL BE THE VALUE OF Q WHEN SEL = 0? The Synthesizer will not be able to determint the value of Q when SEL = 0. Therefore: WILL RETAIN THE VALUE OF Q! (by default will consider else Q<=Q;) THEREFORE: WILL INFER A TRANSPARENT LATCH!

Slide 68 1 INCOMPLETE ASSIGNEMNTS in combinational always statements: Example: module CORRECT1( input A, input B, input SEL, output reg Q); (A or B or SEL) Q <=B; if (SEL) Q<=A; endmodule SIGNALS ARE GETTING THEIR NEW VALUE AT THE END OF THE ALWAYS STATEMEMNT! (Their value can be read only after the always statement is ended and relaunched) In tis case, XST CAN DETERMINE THE VALUE OF Q when SEL=0, so it will infer a multiplexer!

Slide INCOMPLETE ASSIGNEMNTS in combinational always statements Same for the code below (the more known version) module CORRECT2( input A, input B, input SEL, output reg Q); (A or B or SEL) if (SEL) Q<=A; else Q <= B; endmodule So, if possible, for describing simple logic, use assign! Less lines to write In the case of an incomplete assignment the syntax checker will generate an error: assign Q = (SEL==1) ? A;

Slide INCOMPLETE ASSIGNEMNTS in combinational always statements Note: The following is also an incomplete assignment! Example: module AND_2( input A, input B, output reg F); (A or B) if (A&&B) F<=1; else F <= 1; //It should be 0! //This can be from a typo! endmodule Keep in mind, that the Synthesizer MINIMIZES!

Slide INCOMPLETE ASSIGNEMNTS in combinational always statements The synthesizer minimizes! Generally: For an input that is NOT READ, it means that is NOT USED. The synthesizer generates a warning message such as: WARNING:Xst:647 - Input is never used. Note A signal is read also in a condition, such as if (B)…., or (B==1), not only …<= B;! For an output which NEVER CHANGES during circuit operation, the synthesizer generates a warning such as: WARNING:Xst:xxxx – Output Q never changes during circuit operation. Q is connected to VCC Or: WARNING:Xst:xxxx – Output Q is constant Or, if Q changes during circuit operation ONLY ONCE: WARNING:Xst:xxxx – The register/latch FDXX hinder the constant Q cleaning in line XX

Slide INCOMPLETE ASSIGNEMNTS in combinational always statements The synthesizer minimizes! WARNING:Xst:xxxx – The register/latch FDXX hinder the constant Q cleaning in line XX This can happen when Q is initialized to a value and then in the circuit is set to another CONSTANT value Example: reg Q = 0; (posedge CLK) //even for sequential statements, //because Q will change only once! Q <=1; Q will be 0 at the beginning and then constantly 1! Where is the greatest danger of making constant outputs? Look carefully at the shift register code!: Shift left: Q <= {Q[6:0], In} or Q <= {Q[7:1], In} ? Shift right: Q<= {In, Q[7:1]} or Q <= {In, Q[6:0]} ?

Slide INCOMPLETE ASSIGNEMNTS in combinational always statements The above examples are relatively simple and the mistake is visible But do you like to use nested if statements? Example: * begin if (A) if (B) begin if (C) Q<=3’b010; end else Q <=3’b000; //else for which if? //it is else for if (B) //What if C = 0? It will infer a LATCH else if (B) Q<=3’b111; //this else goes then to which if? //to if (A) else if ….//and this one…? // to else if (B)! ALIGN “elses” to “ifs”! Better: Concat A, B, C into a bus and use assign or case Sometimes, nested ifs can not be avoided. Example: Transform an 8-bit counter to a 2-digit BCD counter (LAB exercise!)

Slide INCOMPLETE ASSIGNEMNTS in combinational always statements Frequently appear in CASE statements The “default” statement is not enough! Example: Logic describing transitions to a state machine: StC represents the currents state, StN the next state * begin case (StC) Idle: if (In1) StN <= St1; else StN <= Idle; St1: if (!In1) StN <=St2; //HERE IS NO ELSE! //THE SYNTHESIZER WILL INFER A //LATCH FOR StN! St2: StN <= St3; St3: if (In2) StN <= St2; else StN <= Idle; endcase

Slide INCOMPLETE ASSIGNEMNTS in combinational always statements Frequently appear in case statements Solution that also allows for more compact description * begin StN <= StC; // by default, STAY IN THE CURRENT //STATE case (StC) Idle: if (In1) StN <= St1; St1: if (!In1) StN <=St2; St2: StN <= St3; St3: if (In2) StN <= St2; //here are two choices, we need else else StN <= Idle; default: StN <= Idle; //default DOES NOT TOTALLY SOLVE // INCOMPLETE ASSIGNMENTS, only for the CASE branches! // It also helps for safe implementation of a state machine endcase

Slide INCOMPLETE ASSIGNEMNTS in combinational always statements Why important to avoid? Because can lead to inference of unwanted latches One reason for simulation differences between behavioral and post-translate A latch is a memory element, it will not always act as a combinational circuit! The syntesizer generates a warning message: WARNING:Xst:xxxx – Found x-bit latch for the signal StN LATCH este asynchronous. XST does not recommends asynchronous circuits! If the designer wants to intentionally generate latches, the warning message can be ignored Otherwise, review the code

Slide 77 Note: Incomplete assignments in Sequential always statements Example: (posedge CLK) if (Reset) Q <= 0; else if (CE) Q<=Q+1; What happens with Q if Reset = 0 and CE = 0? The counter will hold i.e. keeps its value No latch will be inferred, because anyway a register is inferred for the counter Incomplete assignments are allowed in sequential always statements Used to describe the role of the “Clock Enable” types of signals

Slide 78 1.Make INCOMPLETE ASSIGNMENTS 2.Exclude based on the SENSITIVITY LIST 3.Make COMBINATIONAL LOOPS Why these are not treaten as an error by the synthesizer? DO NOT: Verilog for Synthesis: Combinational always statements

Slide 79 DO NOT use the sensitivity list to exclude a signal! Example: We want to read the value of a signal ONLY WHEN another signal changes (B will be read only when A changes) (A or C) //The always statement will not be executed //by the simulator when B changes Q<=(!C) | (A AND B); Behavioral Simulation Result: B=0 but still Q=1 CAN BE PRACTICALLY MADE SUCH A CIRCUIT, WITHOUT USING A MEMORY ELEMENT (i.e. REGISTER)? Excluding signals based on the SENSITIVITY LIST

Slide 80 DO NOT use the sensitivity list to exclude a signal! Example: We want to read the value of a signal ONLY WHEN another signal changes (B will be read only when A changes) (A or C) //The always statement will not be executed //by the simulator when B changes Q<=(!C) | (A AND B); Synthesis result: Post-Translate simulation result: Q changes no matter whether B changes or not Excluding signals based on the SENSITIVITY LIST

Slide 81 DO NOT use the sensitivity list to exclude a signal! Example: We want to read the value of a signal ONLY WHEN another signal changes (B will be read only when A changes) (A or C) //The always statement will not be executed //by the simulator when B changes Q<=(!C) | (A AND B); Synthesis result: During synthesis: WARNING:Xst:819 - c:/temp/test1/combinational.v line 21: The following signals are missing in the process sensitivity list: RECOMMENDATION: INSERT IN THE SENSITIVITY LIST ALL OF THE SIGNALS READ IN THE ALWAYS STATEMENT! This is a NECESARRY CONDITION for Behavioral and Post-Translate simulations to produce the same result! Simplified solution: * Excluding signals based on the SENSITIVITY LIST

Slide 82 1.Make INCOMPLETE ASSIGNMENTS 2.Exclude based on the SENSITIVITY LIST 3.Make COMBINATIONAL LOOPS Why these are not treaten as an error by the synthesizer? DO NOT: Verilog for Synthesis: Combinational always statements

Slide 83 Example: module Test( input [3:0] A, output reg [3:0] Q); (A or Q) Q<=Q + A; //Clearly a Combinational Loop From the simulator’s point of view: the always statement will run in an infinite loop (after finishes, Q changes, so the always statement is run again) If A is not 0, the Q immediately reaches its maximum value The Behavioral simulator will hang or issue an error But the circuit CAN BE SYNTHESIZED, EVEN WITHOUT A WARNING! The generated circuit is obviously useless (positive fedback – a latch?) The Post-Translate and Post-Route simulators will not be able to determine the value of Q, the output value will be always XXXX AVOID COMBINATIONAL LOOPS!!! Combinational Loops

Slide 84 Everybody can avoid a combinational loop such as below: Q<=Q + A; HOWEVER: What about in a longer code? (A or B or C) begin … A<= B & … end …………. (B or Q or C) begin … B<= Q | C |… end …………… (Q or A or C) begin ….. if (A==…) Q<= end //A depends on B, B depends on Q and Q depends on A! It is a loop! What do you want to describe here? Try to clear up first the combinational logic You want to describe, then start writing the code! Combinational Loops

Slide 85 Note: Loops can be made in sequential always statements. In this case registers are inferred for keeping the value of Q: (posedge CLK) begin Q<=Q + A; Synthesis result : Behavioral and post-translate simulation result: Counter with increment of A Combinational Loops