EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Pei-Chen Chiu On-behalf of the TPS Feedback Team NSRRC, Hsinchu, Taiwan Power Supply Control Interface and Orbit Feedback Environment for TPS

2 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Outline TPS Power Supply & Control Interface Integrated Orbit Feedback System Infrastructure Corrector Control Interface BPM & Feedback Engine Interface Summary

EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Power Supply and Control Interface

4 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Storage Ring Dipole PS Parameters Unipolar Type Maximum current 750 A Nominal voltage rating850 V Current control range A Current Stability (100 s to 8 hours) ±10 ppm Award to IE Power Control Interface Ethernet (similar with CLS) Storage Ring Quadrupole PS Parameters Unipolar, switched-mode Maximum current rating250 A Nominal voltage rating30 V Current control range A Current Stability (0 to 8 hours) ±2.5 mA p-p Contracted to Chroma ATE Inc Control Interface Ethernet (LXI compatible) Storage Ring Power Supply (1/2)

5 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Storage Ring Sextupole PS Parameters (Include Transport line Magnet PS) Unipolar, switched-mode Maximum current rating 250 A Nominal voltage rating 30 V Current control range A Current Stability (0 ~ 8 hours) ±12.25 mA p-p Contracted to Chroma ATE Inc Control Interface Ethernet (LXI compatible) Storage Ring Power Supply (2/2)

6 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Booster Ring Power Supply Booster Dipole PS Parameters Quadrant operation (Voltage bipolar, current unipolar) Typical waveform 3Hz biased sine wave Maximum peak current 1200 A Nominal peak voltage(option1/2) V Current control range A Current Stability (100 s to 8 hours) ±10 ppm Award to IE Power Control Interface Ethernet (similar as CLS) Booster Quadrupole PS Parameters Quadrant operation (Voltage bipolar, current unipolar) Typical waveform 3Hz biased sine wave Maximum peak current 120 A Nominal peak voltage(option1/2) V Current control range 1-120A Current Stability (100 s to 8 hours) ±10 ppm Award to IE Power Control Interface Ethernet (similar as CLS)

7 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Storage Ring: Corrector, Skew Quad Power Supply Booster: Corrector, Sextupole Power Supply LTB, BTS: Corrector Power Supply Corrector & BR Sextupole PS Parameters Bipolar, switched-mode Maximum peak current ± 10 A Nominal peak voltage(option1/2) + 48 V Current control range -10~10A Noise level< 100  A Current Stability (0 ~ 8 hours) ± 100  A p-p Manufactured by Industrial Technology Research Institute Control Interface Analogue interface Storage Ring Slow Corrector (± 600  rad) noise level < 5 nard (< 10 ppm)

8 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Interlock PLC IOC EPICS IOC ADLINK cPCI CPU ADLINK 128 Bits DI/DO TEWS TCP201 IP Carrier Hytec IP ADC 24 bits, 16 channels IP-ADC-8417 EVR (CPCI6U-EVR-300) Trigger Fanout Trigger Ramp Trigger TPS Control Network Hytec IP DAC 18 bits, 16 channels IP-DAC-8415 BR frev clock 3 Hz Power supplies trigger EPICS IOC ACQ164CPCI 24 bits ADC, 32 ch, GbE Sextupole SD, SF PS Ethernet Switch Ethernet Interface: On/Off control Status readback Interlock reset Two Options: Analogue Reference Input (Waveform) or Embedded Waveform Generator Booster Dipole, QF, Q1, Q2, QM PS (IE Power Inc.) Booster Main Power Supply Control Interface

9 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 TPS Control network Cell Power Supply Control cPCI IOC Ethernet Switch Quad (10), Sextupole (7) (Chroma ATE Inc.) x 24 EPICS Access (10 Hz rate) Orbit Feedback Setting (10 kHz rate) CPU Module ±10 Amp Power Supplies (ITRI) EVR (cPCI-EVR-300) Corrector Power Supply Controller (CPSC) SR Slow Correctors 168 (H) +168 (V) SR Fast Correctors 96 (H) + 96 (V) Skew Quadrupole 96 BR Correctors 60 (H) + 36 (V) EPICS IOC 20 bits DAC 24 bits ADC (D-Tacq) CLK/Trigger Dipole PS (IE Power) x 1 SR Power Supply Control in one Cell

EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Integrated Orbit Feedback System Infrastructure

11 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 TPS Slow and Fast Correctors for one Cell Slow Correctors Fast Correctors CV/CH CV/CH CV/CH CV/ CH CV/CH CV/CH CV/CH Boundary Conditions: Al Chamber (4 mm in thickness) 7 BPM/cell (more will add in future) 7 slow horizontal and 7 slow vertical corrector 4 fast horizontal and 4 fast vertical corrector

12 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 BPM Arc BPMStraight BPM (Primary BPM) Racetrack chamber Courtesy by Vacuum Group

13 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Fast Correctors Slow Correctors SR-SM (S4) Winding on sextupole magnets Horizontal 7 x 24 = 168 Vertical 7 x 24 = 168 Horizontal 4 x 24 = 96 Vertical 4 x 24 = 96 Mount on Bellows to achieve required bandwidth. 13 SR-SM (S3) SR-SM (S2)

14 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 BPM electronic & IOFB module  Platform : Libera Brilliance+  Feedback Engine implemented in IOFB module Grouping and IOFB module

15 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011  SOFB at beginning, then FOFB later, running FOFB only!  SOFB and FOFB running as two independent system with frequency dead-band. FOFB run from DC, a slow system receives the fast correctors from their DC part to prevent saturation. SOFBSOFB FOFB  Orbit feedback system with combined fast and slow correctors BPMs Fast control rules Slow control rules Fast corrector Accelerator Response Golden Orbit Slow corrector Accelerator Response IOFB SOFB + FOFB FOFB  Only FOFB TPS Infrastructure for IOFB

16 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Required Elements for IOFB 7 x 24 BPM 7 x 24 slow horizontal corrector + 7 x 24 slow vertical corrector 4 x 24 fast horizontal corrector + 4 x 24 fast vertical corrector 2 x 24 IOFB modules (one for slow correction loop; one for fast correction loop) 3 x 24 CPSC modules (one for slow horizontal corrector interface; one for slow vertical corrector interface; one for fast horizontal and vertical corrector interface) Each cell (of 24 cells) should have 2 Brilliance+ platforms equipped with IOFB modules + 3 CPSC.

17 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 TPS Control System Control Network TPS Ring Cell 1 3 CPSC s+ PSs 10 kHz rate interface. Each cell has 2 links. One for slow hor. and ver. loop. One for fast hor. and ver. loop Power supply EPICS CA On-line modeling computer Master Clock Path length compensation BPM Group 1 XBPM Electronics 1 XBPM Electronics n BPM Group 2 XBPM Electronics 1 XBPM Electronics n BPM platform 1 IOFB module 1 BPM Group 24 XBPM Electronics1 XBPM Electronics m Timing Master IOC Rocket I/O grouping link BPM soft IOC BPM platform 2 IOFB module 2 BPM platform 1 IOFB module 1 BPM pltform2 IOFB module 2 BPM platform 1 IOFB module 1 BPM platform 2 IOFB module 2 Cell 2 3 CPSCs+ PSs Cell 24 3 CPSCs+ PSs Infrastructure Related BPM Control Diagnostic IOC Group BPM Output

18 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Simulated noise sensitivity function of the corrector VC014to bpm BPM011. Simulation Results 3 dB B.W. ~ 500 Hz

19 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 A Kick Change Simulation Results  Capability of OFB to suppress perturbation could be up to 20 dB for slower noise.  Corrections of fast correctors is almost less than plus/minus 0.05 urad at final, which is smaller than correction of slow correctors

EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Corrector Control Interface

21 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Corrector Power Supply Interface  Analogue interface  Choose 20 bits DAC  Tested prototype Remote DAC setting (DAC installed at cPCI crate) Analogue sum (DC orbit correction + feedback compensation)  Difficult to achieve better than 17 bits performance. Thus, it decided to install the DAC/ADC as closed as power supply as possible.  DAC/ADC interface and PS put at the same crate.

22 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, hour test of 20bit DAC (AD5791) (Full range +/- 6.6V) 6 count

23 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Temperature Effect on DAC output 5 ℃ change=> 80 uV drift 16 uV(~1count)/ ℃

24 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Linearity test 12.6 uV step change  σ=0.047 uV  (less than 0.01 count) Each step: 1 count (~12.6 uV) settings

25 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 D-TACQ 18 bits DAC Module Output Test at Equipment Area Measurement Comparison In the equipment site, it has more obvious power line noise. 1 count increasing

26 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 D-TACQ AO32 18 bits DAC Module & 20 bits DAC Evaluation Module Output Comparison

27 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Use D-TACQ AO32 18 bits DAC Module Output as Reference Input of Power Supply Module (Two separated rack, through 12m cabling) When connect to power supply, due to power-ground isolation, long-cabling induced noised and etc., the performance is deteriorated. The -80 dB noisy level is much higher than acceptable -106 dB. 1 mA (~ 60 nard) 100  A (~ 6 nard) 10  A (~ 0.6 nard)

28 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, bit DAC Setting Power Supply Test Insert into PS crate slot 0 First modulesSecond modules Reference I monitor 10  A 100  A 1 mA (~ 60 nard) 10  A 100  A 1 mA (~ 60 nrad)

29 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Corrector Power Supply (± 10 A) 29 With Corrector magnet Load Current output Amplitude v.s. Frequency 29

30 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Corrector Power Supply Controller (CPSC) + Slow Setting Buffer External Clock (Up to 10 kHz Fast Setting Clock) DO (LEMO connector, for timing measurement), Trigger out, Package received Write Registers 8 bit DO Setting Buffers Gigabit Ethernet Slow Trigger (on demand, may not necessary) Heartbeat Register Rx Fast Setting Ports (GbE, UDP/IP), Through Port Heartbeat Register AURORA 8 Ch, 20 bit DAC Single Board Computer (Linux, EPICS IOC) Status Registers 8 bit DI 24 ch, 16 bit ADC 8 ch, 24 bit ADC (10 kHz Sampling) Slow Access (~ 10 Hz) Control and Status Registers Ethernet Interface (Hardware UDP Stack) 96 pin DIN61412 Connectors x 2 +/- 15 V + 5 V 4 ways, 8 ch adder ~8 x 64 k x 32 bit Waveform Memory Sequencer 10 kHz clock Waveform Memory 10 Hz rate data Trigger (3 Hz) Precise digital temperature sensors Individual Channel Enable/Disable? 10 kHz rate waveform Control and Status Registers Slow Access (~ 10 Hz) Rx Tx Fast Setting Port, Through Port (AURORA) Tx SFP Port

31 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Block Diagram of CPSC IOFB correction ID fast compensation

EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Feedback Engine Interface

33 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Requirement for IOFB modules 1.Data Concentration of BPM data (X, Y, Sum, Status/Counter) and support up to 256 BPM/pBPM. (utilize SFP1 & SFP2) 2.Configurable 2 SFP output. (utilize SFP3 & SFP4) Output of grouped BPM/pBPM data via UDP/IP over GbE or customized AURORA protocol. Output of grouped magnet correction data via UDP/IP over GbE or customized AURORA protocol. Both of AURORA/GbE and BPM/magnet correction could be configured. 3.Inverse Response Matrix Calculation Inverse matrix coefficient could be set by EPICS CA. Corresponding magnet ID according to matrix could also be set by EPICS CA. Golden orbit set by EPICS CA too. 4.PI controller for different eigen-modes tap FIR. 6.Trigger mechanism

34 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Infrastructure of IOFB modules LVDS RX form 4*RAFs LVDS TX to TIM custom out 4*BPM data SFP1 Grouping ??? Orbit Data (168 BPM, X and Y) + Golden Orbit (X and Y) - 20 tap filters n*PID controllers On/Off  M(m*1) = R -1 *  p (n*1) dp Magnet/BPM AURORA/GbE Magnet/BPM AURORA/GbE SFP2 SFP3 SFP4 Output Mapping?

35 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Interconnection within Cell’s CIA To Cell N-1 CPSC for slow horizontal corrector 7 CPSC for slow vertical corrector 7 CPSC for fast horizontal and vertical corrector For diagnostic Group 14*Magnet output Group 8*Magnet output Group 168*BPM output repeater Reserve for future expansion ( such as pBPM input?) To Cell N+1

36 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 IOFB algorithm (1/2) There are total 4 response matrix: sRx,sRy,fRx,fRy. These four matrix will be decomposed by SVD. For example, Slow horizontal response matrix  x =u x Σ x v x T Therefore, inverse response  x -1 =v x Σ x -1 u x T In order to do model space calculation, it is recommended that the IOFB modules should be allowed to download off-line the respective three elements: v x, Σ x -1, u x T Where u x T is 168*168 matirx(168 BPM),, Σ x -1 is 168(or less than 168) array, and v x is also 168*168 matirx Since the IOFB is a kind of the distributed system, the calculation is also distributed. For example, for the 7 slow horizontal correction of the first cell. It is calculated as,

37 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Since TPS has 168 BPM and 168 slow correctors, there are 168 mode for slow loop in IOFB calculation and 96 mode for fast loop. For the 4 fast horizontal correction of the first cell. It is calculated as, The slow and fast loop would be calculate in two separate IOFB modules. For slow loop, it should know Ux(168*168) and Uy(168*168), Sx, Sy(each mode weights), 168 mode PID coefficient, and submatrix of Vx(7*168), Vy(7*168) For slow loop, it should know the first 96 mode of ux(96*168) and uy(96*168), sx, sy(each mode weights), 96 mode PID coefficient, and submatrix of vx(4*96), vy(4*96). IOFB algorithm (2/2)

38 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Block diagram UTUT V Accelerator BPM Corrector Reference Orbit Measured Orbit + Measured Noise + Orbit Disturbance due to various sources Orbit + - Response Matrix R = U*  * V T Vacuum Chamber PID*  -1 Slow loop:168*168 Fast loop:96*168 Slow:168 Fast: 96 Slow:168*168 Fast: 96*96 IOFB coefficient

39 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Different size of response matrix calculation = n m 1.For the fast loop of the first cell, the IOFB should have 4 vertical fast magnet and 4 horizontal fast magnet. 2.For the slow loop of the first cell, the IOFB should have 7 vertical fast magnet and 7 horizontal fast magnet. 3.Support sizable matrix calculation or fixed to maximum configuration (unused part padded with zero).

40 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 BPM ID & Magnet ID 1.BPM ID: 1~168 2.Magnet ID:  Beside IOFB, the global application is also considered. Ex, corrector response measurement, insertion device compensation.  Therefore, distinct Magnet ID is required for all correctors 168*2+96*2=528 According to response matrix, output should be ordered and assigned a magnet ID.  Magnet ID number is depended on the, classified, location and order. Such as, Horizontal fast corrector 23 th cell 3 rd correctorMagnet ID Format

41 EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Summary  Overview of TPS power supply control  Feedback system infrastructure.  BPM and corrector interface.  Corrector power supply controller (CPSC) were contracted to D-Tacq.  I-Tech award the contract of BPM platforms.  Specifications for integrated orbit feedback (IOFB) FPGA modules are still on going.  Communication between CPSC and IOFB modules are in proceed now.

EPICS 2011 Spring Meeting, Hsinchu, June 13-17, 2011 Thanks for Your Attention!