Memory Technology and Interfacing. Stored Program Model Memory Output Input CPU Stored-program computer model.

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Presentation transcript:

Memory Technology and Interfacing

Stored Program Model Memory Output Input CPU Stored-program computer model

Types of Memory Random-Access Memory (RAM)  Volatile  Store data or programs that can be conveniently reloaded Read-Only Memory (ROM)  Non-volatile  Programming once  store essential programs

Random-Access Memory (RAM) Any of its contents may be accessed at any time. (Why this notation is used?) Two technologies are used:  Static RAM (SRAM)  Dynamic RAM (DRAM)

Static RAM A static RAM stores a bit of information within a flip-flop. 6-Transistor SRAM Cell bit word

Dynamic RAM A DRAM stores a bit of information as a charge. row select bit

DRAM vs SRAM DRAM is much higher density (less transistor is used for a cell). DRAM needs to be refreshed every now and then (to prevent memory loss).  Must incorporate with extra (complicated) circuit for refreshing.

ROM Technologies Pure ROM PROM (User-Programmable ROM) EPROM (Erasable PROM) EAROM (Electrically-Alterable ROM)

Pure ROM A mask-programmed ROM made from manufacturer. High cost – need to be produced for large volumes.

PROM Can be programmed (once) by user.  Using PROM programmer. It’s a fusible-link PROM  each cell is fuse (nichrome or polysilicon).  Originally, all rows and columns are connected (logical 0s).  Once a cell is ‘burnt’, it becomes logical 1.  “Grow back” problem  reliability problem. Once programmed, it can not be altered ever again.

EPROM Can be reprogrammed a number of times using a programmer machine. Two main types:  UV-erasable  Electrically-erasable

EAROM Can be read from and written to. It actually is non-volatile RAM. Now, we use Flash Memory

Accessing Memory There must be a control bus for the following operations:  Read data from memory  Write data to memory  Do not access memory

ROM Interfacing

ROM Read

RAM Interfacing

Reading from the Memory (RAM)

Writing to the Memory

Memory Interfacing Design & Memory Map 4K 2 0 =1 2 1 =2 2 2 =4 2 3 =8 2 4 = = = = = = = = = = = = = h 0FFFh 1000h 1FFFh 4K 2000h 2FFFh 4K E000h EFFFh F000h EFFFh

Use Decoder (i.e )