Nanotechnology for Future Generation Devices for Computation and Communication Computation (Magnetic Data Storage, CMOS Technology)‏ Communication (Interconnects)‏

Nanotechnology: Magnetic Data Storage History of the Hard Drive Nanomagnetic Devices and Technologies

01/18/083 Magnetic Storage technologies Tape: serial storage, serial access Disk Drive: semi-serial storage, semi-random access. RAM: “addressable” Random access memory

01/18/084 Magnetic Tape based storage From the Poulsen’s telegraphone: Magnetized piano wire on a cylinder. To the modern cassette tape. Biggest drawback is it is serial storage, serial access. (ca. 1898)‏ (ca. 2006)‏

01/18/085 Magnetic Core Memory Developed in early 1950’s at MIT write: Ampere’s Law read: Faraday’s Law Early example of magnetic cross-point memory Core memory stack $10k/8kb (52 Kb in 8x8x8 inch cube)

01/18/086 The hard disk drive Moving read-write head Magnetic media platter Nonvolatile, slow but for large amounts of cheap storage

01/18/087 The read-write head

01/18/088 The present: hard drive media Longitudinal recording media, deposited by PVD. Areal density limited by bits placed end-to- end.

01/18/089 Progress in HDD vs DRAM (cf. Hitachi)‏

01/18/0810 The future: patterned media 50nm patterned CoCrPt nanopillars with perpendicular anisotropy for > 250Gbits/sqin. (M. Sharma, IIT Delhi)‏

01/18/0811 The Future: Magnetic RAM Nonvolatile No cycle limitation (not so in Flash)‏ Low power (and low voltage)‏ Fast (nsec speeds)‏ Simple bit cell thin film memory cell small area can use multiple memory layers CMOS compatible low processing temperatures embedded applications

01/18/0812 Circuitry Nonvolatile No cycle limitation (not so in Flash)‏ Low power (and low voltage)‏ Fast (nsec speeds)‏Design at HPL, Fab 1Mbit array in 1999, 18 column slices (16 data, 2 parity)‏ Process for 130nm MRAM bits most aggressive in industry. => 1Gb MRAM in includes Cu cladded conductors. HP MRAM 3-conductor MRAM Finished CMOS die Final CMOS wafer (M. Sharma, work done at HP Labs)‏

Nanotechnology: CMOS Technology CMOS Scaling for transistors Lithography for sub-100nm devices Gate Oxide Issues Capacitors for Memory Interconnect Scaling

Introduction The ITRS Roadmap as a “how-to” guide for preserving Moore’s Law These “how-to’s” have included improved photolithography and some device and process modifications; there are some new ones! The first fundamental physical limitation encountered in device scaling has been hit; gate oxide thickness.

Moore’s Law The number of transistors per chip quadruples  every two years (1965)  every three years (1975)  every four years (1995)‏

Why scaling ? P static = I leakage · V DD P dynamic = C L ·V DD · f 2 PDP = C L · V DD 2 Power-delay product Example: CMOS inverter GN D V DD GN D C L ~ C ox *W*L V OU T V IN CLCL V DD t ox Scaling improves density, speed and power consumption of digital circuits

Minimum Feature Size Trend: Limited by Photolithography L GATE 0.7x per generation L GATE Reproduced from "MOS Transistor Scaling Challenges, " M.Bohr, in ULSI Process Integration II, The Electrochemical Society Proceedings Series, PV , p. 466 (C. Claeys, et al., Editors). Reproduced by permission of the Electrochemical Society, Inc. DRAM half-pitch (dense)‏

Roadmap-driven Process and Device Development Needs (IEDM 2001)‏ High-k gate dielectrics Performance-power consumption tradeoff Lightly doped, depleted channels: SOI Reduced off-state power loss, higher mobility Raised, low-resistance source-drains Lower parasitic on-state power loss Tunable work function metal gate electrodes Dual-gate MOSFET’s Limiting power consumption is the watchword!

Gate Oxide Need to use High-k gate dielectrics Needs to be very thin And extremely uniform Poly/2.5 nm SiO2/Si Al/ 1nm HfO2/Si (M. Sharma, work in collab. with HP Labs)‏

ITRS Roadmap EOT Projections* 1 10 Equivalent Oxide Thickness (nm)‏ Technology Generation (nm) Trend molecular layer of SiO Trend 1994 – 2001 * 2001 EOT values developed jointly by Osburn with ITRS PIDS TWG Targets become more aggressive with each new Roadmap. For 1997 and beyond, a physical limitation in the use of SiO 2 appears.

Multi-metal-layer capacitors Hirad Samavati et al., “Fractal Capacitors”, IEEE Journal of Solid-State Circuits, vol. 33, no. 12, December 1998, pp R. Aparicio and A. Hajimiri, “Capacity Limits and Matching Properties of Integrated Capacitors”, IEEE JSSC, vol. 37, no. 3, March 2002, pp

Hierarchical Interconnect scaling Delay is limited by wire size. Need different sized wires

Optical Interconnects Chip-Chip Comm. (cf. Intel)‏ On-chip Optical Antennas (M. Sharma)‏ VCSEL's for on- chip comm.

Adding it all up... Metal Gate / High-k dielectric Multilayered capacitors SiGe/Si channel Transistor of the future

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