Muon New Small Wheel sTGC Trigger for Phase I ATLAS New Small Wheel Electronics Workshop Les Houches December 2012 Lorne Levinson L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop1

Balance conflicting requirements Very rare access, congested location, 1Mrad at innermost radius Minimum on-chamber complexity for reliability – But minimum cables to periphery Minimum on-chamber power dissipation Minimum on-chamber radiation tolerant electronics – But want programmable logic to future-proof the design Maximum access to electronics for repair Compatible with Phase II Upgrade Deliver confirmation of a muon candidate to existing Big Wheel architecture 1.05  sec latency, including 500ns for fiber Tight time schedule L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop2

L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop3 New Small Wheel – Strips, pads, wire groups ~322,000 channels – 3.2mm strips – 16 sectors per wheel – each wheel: 8 layers, in two quadruplets – wire groups (not used in trigger, but read out on L1A) – R = 1m to 4.6m, Δz = 30cm – Required to give accurate coords in radius using weighted pulse height averages to find track centroids in each layer

Concept At each BC, find local tracks that point to the Big Wheel to corroborate its coincidences. Pointing to < 1mrad precision is required. This precision is attained by finding the centroid of 3 to 5 3.2mm strips in each layer From the 8 centroids extrapolate to the Big Wheel Use pad tower coincidence to choose relevant strips BEFORE reading them out to the track finder – Reduces bandwidth – Reduces amount of centroid and track finding logic 2 x 4 layers of Micromegas 4 planes of sTGC ~280 mm lever arm ~150 mm lever 4 planes of sTGC L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop4

Pad towers and bands of strips L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop5  Pad-tower coincidence = 3-out-of-4 overlapping pads Physical pads, each layer staggered by ½ pad in both directions Logical pad-tower defined by projection from 4 layers of staggered pad boundaries Pad trigger selects a band of strips under row of logical pads sTGC quadruplet Channels strips pads wire groups End cap130,36822, Total: ~322,000 ~ existing TGC

Centroid algorithm L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop6 Use average of centroids in each quad to define space points R1 & R2 1, 2, or even 3 of the 4 centroids of a quadruplet are omitted in averaging if: –  -ray's: wide (>5 strips) – Neutrons: large charge or wide – Noise: single strip – Pileup, i.e. pulse in a component strip is active before the trigger

How does a muon look in a background environment Need to reject bad individual layer measurements to get good coordinates  -ray neutron L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop7

ASD is being developed by BNL 1 st prototype in test (analog part only) Supports both sTGC & Micromegas – Separate final versions Can be used for strips, pads, wires L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop8 output pulse for the time-over-threshold 25nsec peak time 130nm feature size  rad hard for total dose, design needs to mitigate Single Event Effects Baseline stabilizer Includes ADC and pipeline + derandomizer for readout on Level-1 trigger ASD – Amplifier-Shaper-Discriminator prototype-1, analog part only

Pad trigger Builds tower coincidences from 3-out-4 coincidences in the two quads Identifies which bands of strips should be read out to the centroid logic – Could put the other pads covering the band in veto – Pad signals ideally synchronized to BC clock in the ASD ~1600 (960) pad inputs per large (small) sector – serialized 32:1 by Trigger Data Serializer ASIC & transmitted in 1 BC On-periphery so it can be programmable Provides the BCID tagging of the strip (and wire) data L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop9

L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop10

Read out ASD has pipeline and derandomizer. – Supports a token readout where up to 32 ASDs can share, in sequence, a serial output line (empty ASDs are skipped) A chain of ASDs can be connected to one GBT E-link – Optimize number of chains versus their bandwidth depending on expected occupancy GBTs for read out on Level-1 Accept: – all strip, pad, wire ASDs: 1-2 GBTs for each of 3 multiplets in one 1/16 th  4x16 = 64 fibre links per side from NSW periphery to USA15 – Pad trigger – Centroid finder input (from TDS) and output (to SL) The same GBTs can do the configuration of the ASD and TDS and provide the TTC signals. (Pad Trigger GBT configures Pad Trigger and Router.) There will be a common ROD for the sTGC and MicroMegas. – Platform/technology not yet decided L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop11

BCID synchronization Note that BCID is defined by the pad logic BCID is assigned to strip data in TDS ASIC and pushed thru’ the system No need to synchronize along the path Resynchronized to BC on output to Sector Logic The Router is passive: it merely choses the active channel and routes it to the output optical link GBT cannot be used: its Tx thru’ Rx latency is too high (~175ns) L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop12

L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop13

Centroid finder results 65nsec with 200MHz FPGA clock Cosmic ray test of one quadruplet Trigger demonstrator using Xilinx Virtex-6 evaluation board Custom mezzanine cards to accept the LVDS signals from 8 (16-chan) TGC ASDs, 4 strip + 4 pad layers: – Triggers on 3-out-of-4 pad layers – Calculates Time-over-Thresholds 1ns sampling – Finds 4 centroids 1 – Selects and averages centroids – Sends inputs and outputs to ethernet for recording, playback  Confirms that the output will be in time to the Sector Logic 1 Calculation done with strip number and 12 bits for the fraction of a strip A cosmic ray passing at an angle thru’ a quadruplet.  are the centroids (values on the left) Dashed line is the calculated average. sTGC Electronics Overview, Les Houches NSW Electronics Workshop14L. Levinson, December 2012

Demonstrator Xilinx Virtex-6 ML605 eval board 108 LVDS inputs 4x16 strips 44 pads: 2x(15+7) Trigger from pads ToT: 1Gsamples/s Ethernet output Output: 1ns samples Calculated ToT Centroids Centroid average L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop15 Goal: find centroids of hits from Time-over-Threshold data in <70ns

Latency sTGC Electronics Overview, Les Houches NSW Electronics Workshop 16L. Levinson, December 2012 The table shows the latency from the interaction point, through the precision strip trigger logic for the Inner Layer to the Sector Logic in USA-15. We take as a model the Xilinx Virtex6. All times are estimates except that for the centroid finder which has been measured.

Radiation and SEE tolerance TDS: on chamber  ASIC with TMR (same process as ASD) Pad trigger: on rim, FPGA with TMR should be possible Router: on rim, FPGA with TMR should be possible These devices have no complex internal state (they do have configuration memory) An SEU will typically be cleared on the next clock They can be reset at the BC clock level with minimal loss The TDS-to-Router link: each word is independent and self-identifying; a lost or corrupted word does no persistent damage. Due to its long latency, the Router-to Centroid link is not a GBT. The Xilinx GTX can provide a much lower latency link. Its radiation tolerance needs to be investigated. L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop17

On-chamber power Expect about 10KW on detector Most at 1.2V  8KAmp Deliver 48V to rim of Small Wheel – Then what to do to get 1.2V at the ASICs Point-of-Load DC-DC converters – Radiation & magnetic field Serial powering L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop18

Demonstrate trigger path from ASD into Sector Logic Plan to use prototype BNL ASD, but dynamic range before saturation may not be enough for accurate centroids … Not for studying detector properties and ultimate resolution L. Levinson, December 2012 sTGC Electronics Overview, Les Houches NSW Electronics Workshop 19 Trigger Demonstrator

Thank you L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop20

BACKUP SLIDES L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop21

Demonstrator pad overlap L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop22

Peak-to-time converter Peak of shaped detector pulse is proportional to strip charge Current ASD prototype has a peak detector (for Micromegas) Investigating charge-to-time converter as part of the ASD – External chip would then measure the time (i.e. charge), instead of the time-over-threshold (which is not linear with charge) Advantages – Time is linearly proportional to charge  better centroid – Lower latency don’t need to wait for falling edge to re-cross the threshold L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop23

Pad trigger − 1 per 1/16 th L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop24 Synchronous coincidence as done by Sasaki for Big Wheel coincidences 40MHz delay BCID ASD layer1 layer2 Assignment to BC followed by combinatorial logic: 3-out-of-4 coincidence for each logical tower OR of all towers in a band Priority encode bands so there is one coincidence per Outer/Middle/Inner region Send band ID,  - ID for each of O/M/I to TDS

THRESHOLD FOR FILTER THRESHOLD FOR WIDTH TEST 20 CH x 8 BIT 5 CH WINDOW INPUT SELECTOR LUT 2 18 *(1/SUM) WEIGHTED SUM 1xCH0+2xCH1+3xCH2+4xCH3+5xCH4 WIDTH VALID CENTROID DATA READ DONE CENTROID READY SIGNAL WIDTH TEST DATA READY SUM CH0+CH1+CH2+CH3+CH4 X 8 8 THRESHOLD COMPARATOR LOCAL OFFSET OF 5 WINDOW SIGNALS WITHING 20 CHANNELS 4 20 x 8 5 x 8 + Layer strip signal is valid when it’s 1 to 5 strip wide (2 18 * CENTROID) CENTROID 48 (2 18 * CENTROID) 20 CH x 8 BIT 20 x 8 WIDTH VALID Divide by number of valid CENTROIDS CENTROID 48 (2 18 * CENTROID) WIDTH VALID CENTROID 48 (2 18 * CENTROID) WIDTH VALID CENTROID 48 (2 18 * CENTROID) WIDTH VALID SUM of valid CENTROIDS 40 QUADRUPLET CENTROID (2 18 * QCENTROID) 20 CH x 8 BIT 20 x 8 20 CH x 8 BIT 20 x 8 20 CH x 8 BIT 20 x 8 LAYER CENTROID LAYER CENTROID LAYER CENTROID LAYER CENTROID ALGORITHM GENERAL IDEA L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop25

TGC for LVL-1 and precision measurement Each of the so-called TGC packages consists of 4 TGC gaps. – Each gap contains 3.5 mm pitch strips (R), pad-wires (  ) and pads for local trigger. – ~400k independent electronics channels. Time-over-Threshold signals from strips are used as charge info. for precision measurement. – The position resolution with better than 100  m has been demonstrated in test beam. Hardware centroid circuits of ToT signals are used for LVL-1 trigger. L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop26

Bandwidth Choice 1/16th, 1 Endcap 1 of 8 layers Gb/s All sTGC Tb/sReduction Link power Watts continuous 1Gb/s samples of 270K strip channels ,504 on each BC, choose up to 3 groups of 8 strips in 1050, 125 bits per group per BC Not practical today to move the raw data directly to USA15: requires 270Tb/s bandwidth In order to choose strip charges (as e.g. Time-over-Thresholds) to send to USA15, one has to say when, i.e. a trigger. Then, one can also say where. L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop27

Layout issues On rim of wheel Pad trigger logic, 1 module per 1/16 th Trigger router (opto transmitter to USA15), 3x8=24 fibres per 1/16 th GBT (opto transmitter to USA15) for read out, 4 GBTs/fibres per 1/16 th Readout, TTC and DCS Power distribution point, 2 per 1/16 th. Input 48V, output ??On-chamber Cards for ASD and TDS ASICs Cable ring for ASD readout to GBT on rim Cable ring, or star, for trigger to router on rim L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop28

Non-projective towers and bending Large angle tracks can cross to the next radially outward pad as they move away from the IP. There is some bending in the fringe solenoidal field This is handled by: 1.OR’ing all possible pad patterns 2.Increasing the band size and overlapping the bands by 1 or 2 strips in downstream layers – This overlap is defined by the band configuration registers in the TDS ASIC. L. Levinson, December 2012sTGC Electronics Overview, Les Houches NSW Electronics Workshop29