XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 18 February 2010 Martin Postranecky, Matt Warren, Matthew Wing

2 18 February 2010C+C μ TCA Crate Timing Receiver Crate Processor MHz Clock Start/Info/Stop Bunch Veto FEE Status C+C Master FEE C+C Fanout FEE MHz Clk Trigger + Telegram ID Bunch Veto 4 FEE 4 C+C Fanout Slave XFEL Timing Interface Other 1-20MHz? Clock Trig/Data Overview MINIMUM FANOUT REQUIREMENTS : 16 + Fanouts, expandable 3x Outputs ( diff. LVDS, STP/UTP ) 1x Input ( single line, level only )

3 18 February 2010C+C Clock 1) ~99 MHz CLOCK : Integer multiple of the incoming MHz clock Integer multiple of the incoming MHz clock from T.R. : 21x = MHz from T.R. : 21x = MHz 22x = MHz 22x = MHz

4 18 February 2010C+C Fast Commands -1- Three Fast Command Lines : - Fanned out to all FEEs via C&C Fan-outs -Same cable lengths -Individual adjustable delays ??? We could propose to use the "ODELAY" functionality available on Virtex-5 ( and Spartan-6 ) FPGAs, which allows for 0-63 bits of ~75ps delay on each I/O pin ( when using 200MHz clock ) We could propose to use the "ODELAY" functionality available on Virtex-5 ( and Spartan-6 ) FPGAs, which allows for 0-63 bits of ~75ps delay on each I/O pin ( when using 200MHz clock ) As we will have FPGA on each fan-out card, we could propose to use this delay facility on the 3x fast command lines sent out to all FEEs ??? As we will have FPGA on each fan-out card, we could propose to use this delay facility on the 3x fast command lines sent out to all FEEs ???

5 18 February 2010C+C ~ 99 MHz clock Data AC Coupling : Manchester Coding Manchester IEE Data = Clock XOR Manchester Code AC coupling on FEEs : ANALOG ADuM3441 : skew too large => use simple capacitive AC coupling => use simple capacitive AC coupling => requires Manchester coding on both START / STOP and => requires Manchester coding on both START / STOP and VETO command lines VETO command lines

6 18 February 2010C+C Simple capacitive AC-coupling - Requires basic Manchester coding on each of the two fast command lines IN+ IN- 100k 10n +1V2 OUT+ OUT- 10n 10k (x) 4k7 100R 4k7 Simple AC – coupling (x) : ONLY ONE RESISTOR FITTED PER SUPPLY

7 18 February 2010C+C Fast Commands -2- 2A) START-TRAIN / TRAIN-ID / BUNCH-STRUCTURE-ID / STOP Synchronised to the ~99 MHz clock Synchronised to the ~99 MHz clock Fixed phase relationship to the ~4.5 MHz clock Fixed phase relationship to the ~4.5 MHz clock a) START : 1100 = 4 bits a) START : 1100 = 4 bits Start pulse to start about ~ 15 msec ( programmable in Start pulse to start about ~ 15 msec ( programmable in 200 nsec steps ) before the train arrives 200 nsec steps ) before the train arrives b) TRAIN-ID : = 32 bits b) TRAIN-ID : = 32 bits The train number is a unique number. From the DAQ point of The train number is a unique number. From the DAQ point of view it should never repeat and should continuously count up view it should never repeat and should continuously count up => Generated on C&C ( counter ) => Generated on C&C ( counter )

8 18 February 2010C+C Fast Commands -3- c) BUNCH-STRUCTURE-ID : = 8 bits MAX c) BUNCH-STRUCTURE-ID : = 8 bits MAX probably only ~16 patterns for any given run/day probably only ~16 patterns for any given run/day d) CheckSum of b) and c) = 8 bits MAX d) CheckSum of b) and c) = 8 bits MAX - Assume maximum 3000 bunches per train e) STOP : 1010 = 4 bits e) STOP : 1010 = 4 bits Stop pulse at the END OF THE TRAIN Stop pulse at the END OF THE TRAIN 2B) RESET uC : 1001 = 4 bits to reset the FE micro-controller via the FE FPGA to reset the FE micro-controller via the FE FPGA 2C) Reserved : 1111 = 4 bits

9 18 February 2010C+C Fast Commands -4- 3A) VETO BUNCH : Synchronised to the ~99 MHz clock Synchronised to the ~99 MHz clock Adjustable phase relationship to the ~4.5 MHz clock : Adjustable phase relationship to the ~4.5 MHz clock : ( up-to 10 clocks for LPD ) ( up-to 10 clocks for LPD ) a) VETO FOLLOWS command : 110 = 3 bits a) VETO FOLLOWS command : 110 = 3 bits b) BUNCH-ID : = 12 bits b) BUNCH-ID : = 12 bits c) -reserved- : = 4 bits c) -reserved- : = 4 bits 3B) NO VETO a) NO-VETO-FOLLOWS command : 101 = 3 bits a) NO-VETO-FOLLOWS command : 101 = 3 bits b) BUNCH-ID ( ??? ) : = 12 bits b) BUNCH-ID ( ??? ) : = 12 bits c) -reserved- : = 4 bits c) -reserved- : = 4 bits

10 18 February 2010C+C FEEs Status Feedback STATUS FEEDBACK from all FEEs :STATUS FEEDBACK from all FEEs : Each FEE plugged-in & powered-up Each FEE plugged-in & powered-up Status only : OK = ?? MHz clock Status only : OK = ?? MHz clock ERROR = high / low / floating... ERROR = high / low / floating... Can change later to carry more information if required. Can change later to carry more information if required. ( BUT this would need using Manchester coding as well ) ( BUT this would need using Manchester coding as well )

11 18 February 2010C+C Master Input Sockets A, B ( & D, E ) Single RJ45 socket A - Bunch Clock ~4.5 MHz - Train Start Pulse Single RJ45 socket B -External Clock ( 750 kHz – 6 MHz ) - External Trigger Single Lemo 00 socket D - External Clock ( LVTTL / NIM ) ( 750 kHz – 6 MHz ) Single Lemo 00 socket E - External Trigger ( LVTTL / NIM )

12 18 February 2010C+C Output Sockets C1, C2….C8 Block of 8x RJ45 connectors ( Tyco : 2x4 bloc ) either : 8 outputs to 8x Fan-Out cards or : 8 outputs from each Fan-Out card to FEEs

13 18 February 2010C+C Fanout 8 TCP/ IP Local AMC Control To FEE FPGA TR / Machine etc. Signals or inputs from C&C Master Outputs to Fanouts Single integrated prototype card Master PLL etc

14 18 February 2010C+C C+C Master Clock : 2 XTAL MHz Clock from TR LVDS Ext. Clock LVTTL / NIM MHz MPX FEE Clock Local Clock MHz Prog. Delay Standalone Clock MHz Prog. Delay MPX PLL ( 750 kHz–6 MHz ) Prog. Mult/Div PLL

15 18 February 2010C+C C+C Master Trigger + Info Start / Trigger LVDS From TR FEE Start/Info Busy Prog. Delay External Interface Ext. Trigger Trigger Pulse Train ID Bunch Pattern BPID Local Clock ETrigger Pulse SATrigger Pulse SATrain ID SABunch Pattern XFEL Interface Select + Process + Store Standalon e Trigger + Info LUT LVTTL / NIM

16 18 February 2010C+C ICS PLL Demo Board

17 18 February 2010C+C End…..