Logical Effort: optimal CMOS device sizing Albert Chun (M.A.Sc. Candidate) Ottawa-Carleton Institute for Electrical & Computer Engineering (OCIECE) Ottawa, Ontario, Canada Monday March 11th, 2002

1.0 Introduction A method of estimating CMOS circuit delay A set of guidelines for sizing CMOS devices to achieve optimal operation speed (i.e. minimum delay) Concept conceived by Dr. Sutherland and Dr. Sproull, back in 1985 A journal was published by the 2 authors in 1991 [2] Research effort was joined by Dr. Harris later A book was published by the 3 authors in 1999 [1]

2.0 Definition (overall) All devices are assumed to have minimum length All examples assume mobility ratioμ n /μ p = 2 All circuit delays are expressed in terms of t inv, which is the propagation delay of an inverter driving an identical inverter without parasitics d abs = d*t inv “d abs ” is the absolute delay of circuit, and “d” is the relative delay value; in units of “t inv ” delay time “t inv ” depends on the process technology, a typical value of 50ps for a 0.6um CMOS technology [1]

3.0 Single Stage Delay Definition (d, g) Delay consists of a fixed component (parasitic delay “p”) and a product of two scalable components (logical effort “g”, and electrical effort “h”) d = f + p = g*h + p Logical effort “g” indicates MOS width ratio between the logic gate circuit to an inverter of same minimum length 2x x 4x x g = 1 g = 4/3g = 5/3

3.0 Single Stage Delay Definition (h, p) Electrical effort “h” is the ratio between output capacitance to the input capacitance (i.e. authors interpret capacitance with MOS gate width, length is minimum process value) h = C out / C in = W (next stage) /W (this stage) Parasitic delay “p” is the intrinsic gate delay due to its internal capacitance (drain & source regions), independent of transistor size and of the output capacitance it drives Gate parasitic delay value “p” is defined as a relative value based on the parasistic value of an inverter “p inv ”; hence for 2 series inverters of same size, the 1st inverter has an electrical effort of 1

3.0 Single Stage Delay Definition (tables)

4.0 Single Stage Delay Example Ring oscillator has odd number “N” of inverters g = 1h = C out /C in = 1p = p inv = 1d = g*h + p = 2 delay_per_stage = d*t inv = t inv *(1 + p inv ) = 1/(2*N*freq) a transition passes loop twice for 1 cycle of oscillation!!! if p inv is given, then t inv can be obtained from above eqn 0.6um CMOS process, d abs = 2*t inv = 2*50ps = 100ps [1]

5.0 Path Delay Definition (G, H, b, B) Path logical effort “G” is the product of all the logic gate logical efforts along a path (i.e. G = Πg i, i is the i th stage) Path electrical effort “H” is the ratio of the last stage output capacitance to the first stage input capacitance H = C out_last / C in_first Logic gate branching effort “b” is the ratio of the total load capacitance at the logic gate output node to the load capacitance of the “on_path” which we are analyzing b = (C on_path + C off_path ) / C on_path = C total / C on_path Path branching effort “B” is the product of all stages’ branching efforts (i.e. B = Πb i, i is the i th stage)

5.0 Path Delay Definition (HB, D, f stage, D opt ) Relationship between the path_electrical effort, path_branching effort and the logic_gate_electrical effort H*B = (C out_last /C in_first ) * Πb i = Πh i Path delay “D” is the sum of all stage delay “d” D = Σd i = Σg i *h i + Σp i = GH + P Path delay has the minimum value when each stage has the same stage effort “f stage ” f stage = F 1/N = (G*B*H) 1/N = (Πg i *b i * C out_last / C in_first ) 1/N Optimal path delay “D opt ” D opt = N*F 1/N + P = N*(Πg i *Πh i ) 1/N + Σp i

5.0 Path Delay Definition (h iopt, C iopt ) Optimal single stage electrical effort (i.e. minimum delay) f stage = g i *h i = F 1/N h iopt = F 1/N /g i Optimal MOS device sizing due to optimal single stage electrical effort (all devices with minimum length) C in = C out * g i / f stage or W (current_stage) = W (next_stage) * g i / f stage

5.0 Path Delay Definition (table)

6.0 Path Delay Example (3 NANDs & C load ) B = 1 H = C/C = 1G = g 1 *g 2 *g 3 = (4/3) 3 = 2.37 f stage = (G*B*H) 1/N = (2.37) 1/3 = 4/3 D opt = N*F 1/N + P = 3*(2.37) 1/3 + 3(2*p inv ) = 10*t inv Stage sizing (3 rd & 2 nd ) z = C*(4/3)/(4/3) = Cy = z*(4/3)/(4/3) = z = C MOS sizing2x + 2x = Cor2x = C/2 C y z C

6.0 Path Delay Example (3 NANDs & 8C load ) B = 1 H = 8C/C = 8G = g 1 *g 2 *g 3 = (4/3) 3 = 2.37 f stage = (G*B*H) 1/N = (8*2.37) 1/3 = (18.96) 1/3 = 8/3 D opt = N*F 1/N + P = 3*(18.96) 1/3 + 3(2*p inv ) = 14.0*t inv Stage sizing z = 8C*(4/3)/(8/3) = 4Cy = z*(4/3)/(8/3) = 2C MOS sizing (1 st stage)2x + 2x = Cor2x = C/2 sizing (2 nd & 3 rd stage)2x = C2x = 2C 8C C y z

6.0 Path Delay Example (3 NAND & fanout) B1 = 2*y/y = 2B2 = 3*z/z = 3B = B1*B2 = 6 G = (4/3) 3 H = 4.5C/C = 4.5f stage = (G*B*H) 1/3 = 4 D opt = N*F 1/N + P = 3*(64) 1/3 + 3*(2*p inv ) = 18.0*t inv 3 rd stage sizingz = 4.5C*(4/3)/4 = 1.5C4x = 1.5C 2 nd stage sizingy = 3*z*(4/3)/4 = z = 1.5C2x = 0.75C z z z y y C 4.5C start end

6.0 Path Delay Example (NOR-NAND) G = g 1 *g 2 *g 3 *g 4 = 1*(5/3)*(4/3)*1 = 20/9H = 20u/10u = 2 B = 1F = G*B*H = 40/9f stage = F 1/N = (40/9) 1/4 = 1.45 D opt = N*F 1/N + P = 4*(40/9) 1/4 + p inv *( ) = 11.8*t inv 4 th stage sizingz = 20*1/(1.45) = 14 = 3xx = 4.66um 3 rd stage sizingy = z*(4/3)/(1.45) = 13 = 4x2x = 6.5um 2 nd stage sizingx = y*(5/3)/(1.45) = 15 = 5xx = 3.0um 1 st stage sizingC in = 10um = 3xx = 3.33um x 20um gate cap yz 10um gate cap

6.0 Path Delay Example (Inverter stages) G = Πg i = 1B = 1H = C load /C in = 25C/C = 25F = 25 D opt = N*F 1/N + P = N*(25) 1/N + N*p inv 1 inverterD opt = = 25.0*t inv 3 invertersD opt = 3*(25) 1/3 + 3 = 11.8*t inv 5 invertersD opt = 5*(25) 1/5 + 5 = 14.5*t inv stage effort of 3 invertersf stage = (25) 1/3 = 2.9 = h i C CC 25C C C CC CC

7.0 Optimal Stage Number (table)

8.0 Optimal Design Procedure 1) From the table of stage logical effort “g”, compute path effort “F = G*B*H” 2) From the “optimal stage number” table, estimate the optimal number of stages for minimal path delay “N opt ” 3) From the table of logic gate parasitic delay “p”, estimate the minimum path delay “D opt = N*F 1/N + Σp i ” 4) Add or Remove even number of inverters until “N ~ N opt ” 5) Compute the stage effort “f stage = F 1/N ” 6) Start from the last logic gate stage, compute (work backward) the transistor sizes with “C in = C out *(g i /f stage )” Note: “C in ” of current stage is the “C out ” of previous stage!!!

9.0 Conclusions (summary of adv & disadv) Advantages: Simple approach to calcuate a circuit path delay due to logic gate circuit topology “g”, device sizing “h” for current driving capability, and parasitic delay “p” Estimate optimal number of logic gate stages for minimum path delay Disadvantages: Ideal RC model for path delay estimation (derivation in textbook) Overlook optimization of chip area and power dissipation

10.0 References 1) Ivan Sutherland, Bob Sproull, David Harris, “Logical Effort: Designing Fast CMOS Circuits”, Morgan Kaufmann Publishers, ) Sproull, R. F., and I. E. Sutherland, “Logical Effort: Designing for Speed on the Back of an Envelope.” IEEE Advanced Research in VLSI, C. Sequin (editor), MIT Press, 1991