D IGITAL L OGIC D ESIGN I G ATE -L EVEL M INIMIZATION

2 P RODUCT OF S UMS S IMPLIFICATION Simplified F' in the form of sum of products using the minterms marked with 0’s. Apply DeMorgan's theorem F = ( F' ) ' F' : sum of products → F : product of sums

3 E XAMPLE Simplify F =  (0, 1, 2, 5, 8, 9, 10) into (a) sum-of- products form, and (b) product-of-sums form: F(A, B, C, D)=  (0, 1, 2, 5, 8, 9, 10) = B'D'+B'C'+A'C'D a)F(A, B, C, D)=  (0, 1, 2, 5, 8, 9, 10) = B'D'+B'C'+A'C'D b)F' = AB+CD+BD' » Apply DeMorgan's theorem; F=(A'+B')(C'+D')(B'+D)

4 E XAMPLE ( CONT.) Gate implementation of the function of the previous example Gate Implementation of the Function F Product-of sums form Sum-of products form

5 Consider the function defined in Table 3.2. In sum-of-minterm: In product-of-maxterm:

6 Consider the function defined in Table 3.2. Combine the 1’s: F ( x, y, z ) = x  y Combine the 0’s : Taking the complement of F Map for the function of Table 3.2 ' 0

7 D ON ' T -C ARE C ONDITIONS A don't-care term for a function is an input- sequence (a series of bits) that is known never to occur. The designer of a logic circuit to implement the function need not care about such inputs. The value of a function is not specified for certain combinations of variables BCD; : don't care Functions that have unspecified outputs for some input combinations are called incompletely specified functions.

The don't-care conditions can be utilized in logic minimization Can be implemented as 0 or 1 Simplify F ( w, x, y, z ) =  (1, 3, 7, 11, 15) which has the don't-care conditions d ( w, x, y, z ) =  (0, 2, 5). a b c g e d f ? wxyzwxyz abcdefgabcdefg BCD code

9 E XAMPLE ( CONT.) F = yz + w'x'; F = yz + w'z F =  (0, 1, 2, 3, 7, 11, 15) ; F =  (1, 3, 5, 7, 11, 15) Either expression is acceptable Example with don't-care Conditions

10 NAND AND NOR I MPLEMENTATION NAND gate is a universal gate because any logic circuit can be implemented with it Logic Operations with NAND Gates

11 NAND G ATE Two graphic symbols for a NAND gate Two Graphic Symbols for NAND Gate

12 T WO - LEVEL I MPLEMENTATION Two-level logic NAND-NAND = sum of products Example: F = AB+CD F = (( AB)' ( CD ) ' ) ' =AB+CD Three ways to implement F = AB + CD

13 E XAMPLE Example : implement F ( x, y, z ) with NAND gate

14 P ROCEDURE WITH T WO L EVELS NAND The procedure Simplify the function and express it in sum of products; Draw a NAND gate for each product term; the inputs to each NAND gate are the literals of the term (the first level); Draw a single NAND gate in the second level; A term with a single literal requires an inverter in the first level. If it is complemented, it can be connected directly to an input of the second-level NAND gate.

15 M ULTILEVEL NAND C IRCUITS Boolean function implementation AND-OR logic → NAND-NAND logic AND → AND + inverter = NAND OR: inverter + OR = NAND For every bubble that is not compensated by another small circle along the same line, insert an inverter or complement the input literal. Implementing F = A(CD + B) + BC

16 NAND I MPLEMENTATION Implementing F = (AB +AB)(C+ D)

17 NOR I MPLEMENTATION NOR function is the dual of NAND function. The NOR gate is also universal gate. Logic Operation with NOR Gates

18 Two Graphic Symbols for a NOR Gate The function must be simplified in the form of product of sums; Example: F = (A + B)(C + D)E Implementing F = (A + B)(C + D)E Two Graphic Symbols for NOR Gate

19 P ROCEDURE WITH T WO L EVELS NOR The procedure Simplify the function and express it in product of sums; Draw a NOR gate for each sum term; the inputs to each NOR gate are the literals of the term (the first level); Draw a single NOR gate in the second level; A term with a single literal requires an inverter in the first level. If it is complemented, it can be connected directly to an input of the second-level NOR gate.

20 M ULTILEVEL NOR C IRCUITS Boolean function implementation Example: F = (AB +AB)(C + D)

21 E XCLUSIVE -OR F UNCTION Exclusive-OR (XOR) x  y = xy'+x'y Exclusive-NOR (XNOR) ( x  y ) ' = ( x' + y )( x + y' )= xy + x'y' Some identities x  0 = x x  1 = x' x  x = 0 x  x' = 1 x  y' = ( x  y ) ' = x'  y Commutative and associative A  B = B  A ( A  B )  C = A  ( B  C ) = A  B  C

22 E XCLUSIVE -OR I MPLEMENTATIONS Implementations xy'+x'y = x  y = xy'+x'y+xx’+yy’ = ( x'+y' ) x + ( x'+y' ) y ( x'+y' ) = ( xy ) ' Exclusive-OR Implementations

23 O DD F UNCTION A  B  C = ( AB'+A'B ) C' + ( AB+A'B' ) C = AB'C'+A'BC'+ABC+A'B'C =  (1, 2, 4, 7) XOR is a odd function → an odd number of 1's, then F = 1. XNOR is a even function → an even number of 1's, then F = 1. Map for a Three-variable Exclusive-OR Function

24 XOR AND XNOR Logic diagram of odd and even functions Logic Diagram of Odd and Even Functions

25 F OUR - VARIABLE E XCLUSIVE -OR FUNCTION Four-variable Exclusive-OR function A  B  C  D = ( AB'+A'B )  ( CD'+C'D ) = ( AB'+A'B )( CD+C'D' ) + ( AB+A'B' )( CD'+C'D ) Map for a Four-variable Exclusive-OR Function

T HE P ROBLEMS OF C HAPTER T HREE : 3.1, 3.3, 3.4(a, b, c, d), 3.6(a, b), 3.12(a, b), 3.13(a, c), 3.15(a, c), 3.16(a, b), 3.19(a, b)

Chapter Four Combinational Logic 27

C OMBINATIONAL C IRCUITS It consists of input variables, logic gates and output variables. Output is function of input only i.e. no feedback When input changes, output changes (after a delay) n inputsm outputs Combinational Circuits  28

For n input variables, there are 2 n possible combinations of the binary inputs. For each possible input combination, there is one possible value for each output variable. A combinational circuit can be specified with a truth table that lists the output values for each combination of input variables. A combinational circuit also can be described by m Boolean functions, one for each output variable. Each output function is expressed in terms of the n input variables.

C OMBINATIONAL C IRCUITS Analysis Given a circuit, find out its function Function may be expressed as: Boolean function Truth table Design Given a desired function, determine its circuit Function may be expressed as: Boolean function Truth table ? ? ? 30

A NALYSIS P ROCEDURE Boolean Expression Approach F 1 =T 2 +T 3= AB'C'+A'BC'+A'B'C+ABC F 2 =AB+AC+BC T 2 =ABC T 1 =A+B+C F 2 =AB+AC+BC F’ 2 =( A’+B’ )( A’+C’ )( B’+C’ ) T 3 =AB'C'+A'BC'+A'B'C 31

A NALYSIS P ROCEDURE We can obtain the truth table directly from the logic diagram Truth Table Approach A B C F1F1 F2F = 0 T2 = 0 T1 = 0 0 F2 = 0 F’2 = 1 T3 =

A NALYSIS P ROCEDURE Truth Table Approach = 0 = 1 = 0 = 1 = 0 = 1 = 0 = A B C F1F1 F2F

A NALYSIS P ROCEDURE Truth Table Approach = 0 = 1 = 0 = 1 = 0 = 1 = 0 = 1 = A B C F1F1 F2F

A NALYSIS P ROCEDURE Truth Table Approach = 0 = 1 = 0 = 1 = 0 = 1 = 0 = A B C F1F1 F2F

A NALYSIS P ROCEDURE Truth Table Approach = A B C F1F1 F2F B 0101 A1010 C B 0010 A0111 C F 1 =AB'C'+A'BC'+A'B'C+ABC F 2 =AB+AC+BC 36

37 Full Adder Circuit