EE/CS 481 Spring 2008 1Founder’s Day, 2008 University of Portland School of Engineering Project Golden Eagle CMOS Fast Fourier Transform Processor Team.

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Presentation transcript:

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Project Golden Eagle CMOS Fast Fourier Transform Processor Team Sandra Pellecer Neil Tuttle Ziyuan Zhang Advisor Dr. Aziz Inan, Dr. Peter Osterberg Industry Representative Mr. David Dunning Intel

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Agenda Introduction Sandra Pellecer Background Sandra Pellecer Methods Ziyuan Zhang Results Neil Tuttle Conclusions Sandra Pellecer Demonstration Team

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering The Fast Fourier Transform (FFT) Efficient algorithm used to compute the Discrete Fourier Transform Used in digital signal processing Used to analyze, filter, and generate digital signals

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Time Domain Vs. Frequency Domain (MATLAB) Dr. Hoffbeck : fsdemo.m

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering 1Hz sine + 3Hz sine Dr. Hoffbeck : fsdemo.m

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering 1Hz sine + 3Hz sine + 5Hz sine Dr. Hoffbeck : fsdemo.m

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Many sine waves Dr. Hoffbeck : fsdemo.m

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Advantages of the FFT The FFT is faster than the DFT DFT FFT

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Project Description Design CMOS MOSIS chip set to compute Fast Fourier Transform Initial Plan (Summer ’07) –Input signal: 4 samples, 4-bit precision –Output signal: 4 samples, 8-bit precision Final Plan (Fall ’07) –Input signal: 8 samples, 4-bit precision –Output signal: 8 samples, 9-bit precision

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering MOSIS Educational Program (MEP) Nationwide educational grant program Sponsors schools such as Stanford, MIT, and Berkeley to design and manufacture integrated circuits $4,000 grant for this project

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Implementation Challenges FFT requires complex (real and imaginary) numerical computations FFT requires a large number of addition and multiplication operations

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Summer ‘07 Studied FFT Algorithm Completed FFT dataflow diagram Created B2Logic components (adder, multipliers) Connect components and test Completed 4 sample, 4-bit FFT circuit

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Fall ‘07 Completed 8 sample, 4-bit FFT circuit Tested and debugged circuit –Circuit output vs. MATLAB & custom simulation program Completed MOSIS CMOS chip set design by Thanksgiving

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Design Tools B2Logic –Digital schematic capture and simulation B2Logic to ABEL Translator (BAT) –Converts B2Logic files to ABEL for CPLD prototyping B2Logic to L-Edit Translator (BLT) –Automatically creates netlist for CMOS IC

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Design Tools (cont.) L-Edit –Automatically generates chip set layout from netlist MATLAB

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering B2Logic Problems Circuit was too large for B2Logic Split design into two parts

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering MOSIS FFT Chip Set Block Diagram

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Chip 1 Schematic Diagram

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Chip 1 L-EDIT Layout

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Chip 1 L-EDIT Layout

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Chip 1 Pinout

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Chip 2 Schematic Diagram

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Chip 2 L-EDIT Layout

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Chip 2 Pinout

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Technical Details 5V, 1.5 micron process AMI Semiconductor Both IC dies are 5mm x 5mm Both ICs contain about 2,000 logic gates Both ICs contain about 20,000 MOSFETs (transistors)

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Project Block Diagram

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Project Schematic

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering MOSIS CMOS Chips MOSIS CMOS Chips

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Conclusions FFT is an efficient algorithm for computing the Discrete Fourier Transform MOSIS CMOS chip set is intended to improve the speed of digital signal processing algorithms First time the FFT has been successfully achieved as a senior design project

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Future Enhancements Combine into single IC Improve precision Implement pipelining Implement inverse FFT

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Demo Block Diagram

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Infinite Sample FFT (MATLAB)

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering 512 Sample FFT (MATLAB)

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering 128 Sample FFT (MATLAB)

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering 32 Sample FFT (MATLAB)

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering 16 Sample FFT (MATLAB)

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering 8 Sample FFT (MATLAB)

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering 4 Sample FFT (MATLAB)

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Demonstration (8 Sample FFT) Input: 3.6kHz

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering Acknowledgements Mr. Dave Dunning Dr. Joseph Hoffbeck Dr. Aziz Inan Dr. Wayne Lu Dr. Peter Osterberg Sandy Russell Dr. Karen Ward Mosis Educational Program (MEP) Thank You.

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering

EE/CS 481 Spring Founder’s Day, 2008 University of Portland School of Engineering FFT dataflow