PWM UNIT 17 로봇 SW 교육원 조용수

학습 목표 PWM PWM Register 2

PWM Pulse Width Modulation 진폭이 일정한 상태에서 펄스 폭을 증 / 감 하여 신호 를 변화시키는 방법 디지털 출력으로 아날로그 회로를 제어할 수 있음. Duty Cycle : High Level 과 Low Level 간의 비율 3

4 N051 PWM Four PWM Generators, each generator supports One 8-bit prescaler One clock divider ( 1, ½, ¼, 1/8, 1/16) Two PWM-timers for two outputs, each timer includes A 16-bit PWM down-counter A 16-bit PWM reload value register (CNR) A 16-bit PWM compare register (CMR) One dead-zone generator Two PWM outputs. 8 PWM channels or 4 PWM paired channels. 16 bits resolution. Support edge and center aligned modes Single-shot or Continuous mode PWM.

PWM/Capture Clock Source 5

6 PWM Edge Align Mode Duty ratio = (CMR+1) / (CNR+1) Duty = (CMR+1) x (clock period) Period = (CNR+1) x (clock period)

7 PWM Double Buffering Illustration New period (CNR) New duty (CMR) S/W write new period (CNR) And new duty (CMR) First cycle Second cycle

8 Operation of Dead Zone Generator Why need the dead zone control? –To avoid a paired-PWM outputs overlapping on duty-on dur ation. –For example, in Motor Driver application, it needs to avoid t he upper and lower power switch turn on simultaneously. Insert a delay time (dead zone) before duty on at each channel of paired-PWM. 8-bit dead-zone timer from PWM clock.

PWM Register 9

10

PWM Register 11

PWM Register 12

PWM Register 13

PWM Register 14

PWM Register 15

PWM Register 16

PWM Register 17

PWM Register 18

PWM Register 19

PWM Register 20

PWM Register 21

PWM Register 22

PWM Register 23

PWM Register 24

PWM Register 25

PWM Register 26

PWM Register 27