DT Track Finder, Global Muon Trigger, Global Trigger H. Bergauer, L. Boldizsar, M. Dallavalle, Ch. Deldicque, J. Erö, L. Guiducci, A. Jeitler, I. Jimenez Alfaro, P. Hidas, K. Kastner, S. Kostner, A. Montanari,A. Nentchev, B. Neuherz, N. Neumeister, M. Padrta, G. Pellegrini, P. Porth, H. Rohringer, H. Sakulin, J. Strauss, A. Taurok, J. F. de Trocóniz, C.-E. Wulz Bologna, Budapest, Univ. Aut. Madrid and Vienna Groups presented by Claudia-Elisabeth Wulz Annual Review, CERN, 16 Sep 2003

Annual Review, Sep C.-E. Wulz2 Drift Tube Trigger Track Finder Vienna, Madrid, Bologna The Drift Tube Trigger Track Finder system (DTTF) consists of: PHTF - Phi Track Finder Sector Processor (72 boards) - Vienna - new name (formerly called DTTF) ETTF - Eta Track Finder (12 boards) - Madrid, Vienna WS - Wedge Sorter (12 boards) - Bologna TIM - Timing Module (6 boards) - Vienna - same design as for Global Trigger DAQU - DAQ output unit (1+6 boards) - Vienna - muon data to be stored on tape by DAQ DT/CSC Transition Board (24 boards) - Vienna - information exchange between DT and CSC Output Test Board (1 board) -Vienna - only for testing

Annual Review, Sep C.-E. Wulz3 Status of PHTF - Function Evaluation Prototype ready Long term tests performed Tests with ORCA simulation data – One bit error in one track segment (probably broken line in an internal layer) – One assignment error – Clock phase control: 3 states instead of 5 – Further investigations in progress - Four additional PHTF boards are in production Final adjustments were made to layout Individual JTAG access added for each BGA chip (important for the initial phase) PCB with better thermal parameters chosen

Annual Review, Sep C.-E. Wulz4  Matching patterns recalculated (2002) Number of patterns reduced by 25%: Fit neatly into two FPGAs  Pseudo-rapidity assignment: Region covered goes from (-1.3, 1.3) to (-1.2,1.2) Assigned eta now in Station 2 to be consistent with RPC  Quality ordering revised (based on simulation) Prefers one extra segment rather than a high-quality one But might be reconsidered according to June test beam results  New algorithm tested with ORCA_6 New reduced set of patterns slightly more efficient (91% to 93%) Changes to the ETTF algorithm

Annual Review, Sep C.-E. Wulz5  VDHL model done and tested  High-statistics ORCA sample prepared to check VHDL model in event-by-event basis (will follow)  Board design ready, 2 boards in production 8 layers 2 big and 5 small FPGAs – fully reconfigurable (except the connections) same input connection as for PHTF  Integration test with PHTF will follow Status of ETTF

Annual Review, Sep C.-E. Wulz6 ETTF board block diagram ETTF-N ETTF-P Input Synch. -2 Input Synch. Input Synch. 0 Input Synch. +1 Input Synch. +2 Output driver 21 bit hit 21 bit quality 21 bit hit 21 bit quality 21 bit hit 21 bit quality 21 bit hit 21 bit quality 21 bit hit 21 bit quality x3x6 bit Eta Address of Tracks found by positive side PHTFs 3x2x5 bit on Backplane Address of Tracks found by negative side PHTFs 3x2x5 bit on Backplane 4x3x6 bit Eta To Wedge Sorter Optical Inputs

Annual Review, Sep C.-E. Wulz7 Status of Wedge Sorter (Bologna) Board received in August. Description of functionality: Almost finished preliminary electrical test (power, connections, etc). Ready to start the first JTAG tests and preparing the test jig for a full functionality test by using Pattern Units.

Annual Review, Sep C.-E. Wulz8 Status of other DTTF boards - DT/CSC Transition Board Board ready, partly tested FPGA with Range Correction LUT filled in by 1:1 mapping Connection test next week - Output Test Board - Board ready, participates in tests Allows to read out DTTF results in real time with logic analyzer or Input Buffer Board Plugged to the Wedge Sorter back side – selectable PHTF output – GTL+ termination pluggable (remove when WS is in use) - DAQ Output Board first design steps made

Annual Review, Sep C.-E. Wulz9 DTTF Milestones and Schedule DATEITEMSTATUS May 2003:PHTF function evaluation prototype testedbasically done June 2003:DT/CSC overlap testnow: Sept * July 2004:PHTF pre-production prototype (PPP) done on schedule * Dec. 2004:PHTF production done on schedule June 2003:ETTF design done done Dec. 2003:ETTF boards produced on schedule * Sep. 2003:DTTF prototype integration (PHTF,ETTF,WS) foreseen: Dec * June 2003:Wedge Sorter prototype doneready for final tests * July 2004:Wedge Sorter production done on schedule * Nov. 2003:Barrel Sorter prototype donenow: Jan * July 2004:Barrel Sorter production done on schedule (most recent milestone indicated by *)

Annual Review, Sep C.-E. Wulz10 Timing Module PHTF Data source card Result read back card DTTF Test Crate (front)

Annual Review, Sep C.-E. Wulz11 Optical link emulator Output Test BoardDT/CSC Transition Board DTTF Test Crate (rear)

Annual Review, Sep C.-E. Wulz12 Global Muon Trigger Overview Output: 8 bit , 6 bit , 5 bit p T, 2 bits charge/synch, 3 bit quality, MIP bit, Isolation bit Inputs: 8 bit , 6 bit , 5 bit p T, 2 bits charge, 3 bit quality, 1 bit halo/eta fine-coarse Best 4  4  RPC brl 4  DT 4  CSC 4  RPC fwd 252 MIP bits 252 Quiet bits

Annual Review, Sep C.-E. Wulz13 GMT in the Global Trigger Crate Conceptual design ready FPGAs being designed 1 GMT Logic Board 3 Pipeline Sync. Boards 6-channel prototype available 4 DT/CSC + 8 RPC muons Global Trigger Crate Special wide input board parallel to front panel

Annual Review, Sep C.-E. Wulz14 GMT progress since September 2002

Annual Review, Sep C.-E. Wulz15 FPGA Development for GMT Cadence NCSIM Xilinx ISE i Synplify 7.3 VHDL Behavioral simulation Gate level simulation Chip configuration VHDL for look-up tables generated by LUT Framework from C++ representation Synthesis Implementation Concurrent Versions System to manage VHDL code CVS Server “Build System” most of design flow scripted with Makefiles Automated tests verify functionality after every change cross-check with C++ simulation Developer

Annual Review, Sep C.-E. Wulz16 MIP and ISO Assignment FPGA’s Xilinx XC2V3000 –432 chip inputs/outputs –96/96 18 kbit memory blocks used Developed VHDL model Simulated behavioral model & cross-checked with ORCA (NC-SIM) Synthesized using Synplify 7.21 Implemented with Xilinx ISE Simulated chip-level VHDL & cross-checked with ORCA (NC-SIM) GMT Logic Board

Annual Review, Sep C.-E. Wulz17 Logic FPGA’s Xilinx XC2V3000 –464 chip inputs/outputs –92/96 18 kbit memory blocks used Developing VHDL model –95 % complete Synthesized using Synplify 7.21 Implemented with Xilinx ISE –75% of chip resources used To be done –Complete VHDL model –Synthesize/Implement final version –Simulate gate level model GMT Logic Board

Annual Review, Sep C.-E. Wulz18 Generic Handling of GMT Lookup-Tables projection,  -conversion, sort-rank, merge-rank, …  Function calculated at runtime  Memory efficient  All code in ORCA CVS repository ORCA simulation (C++) Lookup() GMT LUT Y Lookup Method GMT LUT X Lookup Method configfile Scales,Parameterizations Global Muon Trigger Simulation LUT Generator Application (C++) COE memory contents LUT2HW tool (C++) LUTfile Save() GMT LUT Y Save Method GMT LUT X Save Method configfile Scales,Parameterizations LUTfile C++ classes represent LUT function Used in ORCA Simulation of GMT Used to generate all files need for firmware implementation XCO DPM RAM definition.EDN.VHD.MIF VHDLwrapper Xilinx CoreGenerator

Annual Review, Sep C.-E. Wulz19 GMT Hardware Status GMT consists of –3 pipeline synchronizing boards… prototype available –1 GMT logic board… logic design completed FPGA design for GMT logic board in progress –Input FPGA (4x)… logic design completed –MIP and ISO assignment unit (2x)… firmware completed (brl+fwd) –GMT logic FPGA (2x)… firmware 95% complete (brl+fwd) –Sorter FPGA (1x) … logic design completed Milestones (unchanged since Apr 2002) –(Dec 01) Dec 02: logic design completed… completed –(Dec 02) Dec 03: FPGA design done… progress as planned –(Dec 03) Jun 04: GMT available… progress as planned –(Jun 04) Oct 04: GMT tested… progress as planned –Oct 04: GMT integration tests start… planned on time –Jan 05: GMT integration tests completed… planned on time

Annual Review, Sep C.-E. Wulz20 Global Trigger Rack

Annual Review, Sep C.-E. Wulz21 All boards on front side. Boards arranged for minimum cable length. Global Trigger Crate

Annual Review, Sep C.-E. Wulz22 VME interface PSB GTL6U GTL_CONV Global Trigger Prototype Crate

Annual Review, Sep C.-E. Wulz23 VME interface MEMORY SYNC chips ROP for DAQ Input module Synchronisation and monitoring of trigger data PSB6U only for the Prototype Crate PSB-6U Prototype Board

Annual Review, Sep C.-E. Wulz24 40, 80 MHz CLK drivers DS92LV16 receivers Registers for 40  80 MHz conversion Infiniband connectors DS92LV16 transmitter for tests new PSB_IN80 for PSB-6U

Annual Review, Sep C.-E. Wulz25 VME interface CONV chips 80MHz GTL+ signals Channel LinkRec +1.5V supply VME to GTL6U GTL_CONV is used only in the Prototype Crate Channel Link signals GTL Conversion Board

Annual Review, Sep C.-E. Wulz26 Calculates 64 trigger algorithms GTL6U will be used in the prototype crate as well as in the final GT-crate GTL-6U Logic Board (right side) VME REC chips COND chips GTL+ signals 4x4 calo objects 4 muons

Annual Review, Sep C.-E. Wulz27 TIM chip TTCrx CLOCK circuits LVDS drivers CLK, BCRES, L1A, RESET to each VME slot VME TIM-6U will be used in the prototype as well as in the final GT and DTTF crates. Front Panel new TIM-6U Timing Module

Annual Review, Sep C.-E. Wulz28 A.T FDL-9U Final Decision Logic VME ALGO bits to DAQ ALGO bits to EVM Final OR bits to TCS Techn.Trigger bits from PSB ALGO bits from GTL FDL chip on MEZZ896

Annual Review, Sep C.-E. Wulz29 TCS-9U Central Trigger Control Board VME FastSigs 24 part‘s + 8DAQ part‘s TCS status to 8 DAQ part‘s L1A,... to 32 TTCvi FastSigs from 8 Emulators TCS_MON chip TCS chipClock EVM+DAQ records

Annual Review, Sep C.-E. Wulz30 bottom side top side 50 Ohm connectors XC2V2000-4FF896C BGA: 1mm pitch, track width=83  m Mezzanine Board (MEZZ896) MEZZ896 will be used in TCS-9U and FDL-9U

Annual Review, Sep C.-E. Wulz31 GCT/GT integration test setup Bristol + Vienna groups, Vienna, July 2003

Annual Review, Sep C.-E. Wulz32 GCT/GT integration test results and plans Link latency 50 ns with 1m cable, 65 ns with 5m cable. Data exchange 64 bits per 25 ns sent over one two-pair Infiniband cable. Different sets of patterns have been programmed at the transmitter end of the link and successfully read from a memory on the PSB. Clock PLL-based clock drivers to stabilize the TTC clock signals can be used. Long term stability Full test still to be made LHC orbits equivalent to bit cycles tested. Further tests Planned in Vienna with boards from Bristol in autumn 2003.

Annual Review, Sep C.-E. Wulz33 GT on-line software C++ test programs exist to run the following boards both stand-alone and as a system : PSB-6U, GTL-CONV, GTL-6U, TIM-6U, TTCvi. The programs are being implemented as XDAQ-plugins. The GT setup definition is planned in.xml format, also to be used by ORCA. We are working on the SETUP program, including on a concept with a GUI.

Annual Review, Sep C.-E. Wulz34 Milestones updated Custom Backplane for VME 9U crate 4 6U Prototype: Channel Links... existsMS 03/02 –9U Backplane: 80MHz GTLp and Channel Links,... design in progressMS 03/03  09/03  12/03 PSB Input board (synchronisation, monitoring) 4 6 channel 6U Prototype: Channel Link receivers... board testedMS 03/02 4 PSB-IN80: DS92LV16 serial receivers... board tested –12 channel board: memories inside FPGAs...conceptual design MS 06/04 GTL Logic board: 4 Conversion board for prototype... board testedMS 03/02 –GTL-6U prototype: 20 channels …hardware is testedMS 06/03 Signal transfer tested with test patterns -> ok… working on firmware XDAQ compatible test program in C++ exists Loading of conditions not tested yet (software under development) –GTL-9U board: 32 channels...conceptual design MS 11/04 4 , 4 isol. e/ , 4e/ , 4 central jets, 4 fwd jets, 4  -jets,  E T, E T mis, H T, 12 jet counts TIM Timing board... board tested MS 06/03  09/04 4 6U size, TTCrx, clock and L1A distribution, also used by DTTF; working on version for new TTCrx MEZZ896 4 Mezzanine boards (used on TCS-9U, FDL-9U)... boards produced MS 06/03 FDL-9U Final Decision board... design in progress MS 06/03  11/03  02/04 TCS-9U Central Trigger Control board... Layout finished MS 04/03  09/03  12/03 GTFE-9U Readout board... conceptual design MS 12/03  03/04  02/05 Global Trigger Status and Milestones Sept. 2003

Annual Review, Sep C.-E. Wulz35 Production, Full Chain and Slice Tests, Integration GTL-6U  hardware ok TIM-6U  09/04 (version for new TTCrx) TCS-9U  09/03  12/03 BACK-9U  09/03  12/03 FDL-9U  11/03  02/04 System test (full chain) of 20-channel GT (without GTFE)  06/04 GT system tests  6/05 Global Trigger PSB-9U  06/04 Integration of GT/GMT with DAQ  01/06 Slice tests performed in Vienna as boards become available. Installation and commissioning in USC55 planned in phase with other subsystems (GCT, regional muon trigger systems) during second half of GTFE  03/04  02/05 GTL-9U  11/04 Global Muon Trigger FPGA design  12/03 Board production  06/04 GMT system tests  01/05 Global Trigger PROTOTYPE BACK-6Uok PSB-6U ok PSB-IN80 ok GTL-CONVok GTL-6U hardware tested (Milestone 6/03) TIM-6U done (Milestone 6/03) - prototype will be used as spare module for final system Integration test with GCTdone (July 2003)

Annual Review, Sep C.-E. Wulz36 Acknowledgements Thanks to the following people for providing transparencies: J. Erö, J. F. de Trocóniz, Ch. Deldicque (DT Track Finder) A. Montanari (Wedge Sorter) H. Sakulin (Global Muon Trigger) A. Taurok (Global Trigger hardware) J. Strauss (Global Trigger software)

Annual Review, Sep C.-E. Wulz37 Summary of main progress DTTF (Bologna, Madrid, Vienna)  track finder function evaluation prototype produced and tested (Vienna)  track finder VHDL model and board design ready (Madrid, Vienna)  Wedge Sorter prototype available (Bologna) Other DTTF boards produced (Vienna) GMT (Vienna) FPGA logic design close to completion GT (Vienna) Logic board produced and tested Timing module produced and tested Layout of TCS module finished All systems (Bologna, Budapest, Madrid, Vienna) On-line software under development ORCA software updated in parallel CMS-Note on SUSY level-1 trigger efficiencies practically ready