FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Topics n Off-chip connections.

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Presentation transcript:

FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Topics n Off-chip connections.

FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Off-chip connections n A package holds the chip. Packages can introduce significant inductance. n Pads on the chip allow the wires on chip to be connected to the package. Pads are library components which require careful electrical design.

FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Structure of a typical package

FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Solder ball connection substrate package solder

FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Package structure n Package body is physical/thermal support for chip. n Cavity holds chip. n Leads in package connect to pads, provide substrate connection to chip.

FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Some packages DIP PGA PLCC

FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Pin inductance n Package pins have non-trivial inductance. n Power and ground nets typically require many pins to supply required current through the packaging inductance.

FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Pin inductance example Power circuit including pin indutance:

FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Pin inductance example, cont’d n Voltage across pin inductance: v L = L di L / dt n Current surge into chip causes inductive voltage drop: –L = 0.5 nH; –i L = 1A; –v L = 0.5 V.

FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR I/O architecture n Pads are placed on top-layer metal to provide a place to bond to the package. n Some advanced packaging systems bond directly to package without bonding wire; some allow pads across entire chip surface.

FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Input pads n Main purpose is to provide electrostatic discharge (ESD) protection. n Gate voltage of transistor is very sensitive—can be permanently damaged by high voltage. n Static electricity in room is sufficient to damage CMOS ICs.

FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Input pad circuits n Resistor is used in series with pad to limit current caused by voltage spike. n May use parasitic bipolar transistors to drain away high voltages: –one for positive pulses; –another for negative pulses. n Must design layout to avoid latch-up.

FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Output pad circuits n Don’t need ESD protection—transistor gates not connected to pad. n Must be able to drive capacitive load of pad + outside world. n May need voltage level shifting, etc. to be compatible with other logic families.

FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Output pad circuit, cont’d.

FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Three-state pad n Combination input/output, controlled by mode input on chip. n Pad includes logic to disconnect output driver when pad is used as input. n Must be protected against ESD.

FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Three-state pad circuit