Ratioed Circuits Ratioed circuits use weak pull-up and stronger pull-down networks. The input capacitance is reduced and hence logical effort. Correct.

Slides:

Advertisements

Similar presentations

ECE555 Lecture 5 Nam Sung Kim University of Wisconsin – Madison

Advertisements

Digital CMOS Logic Circuits

Topics Electrical properties of static combinational gates:

Transmission Gate Based Circuits

Ch 3. Digital Circuits 3.1 Logic Signals and Gates (When N=1, 2 states)

CSET 4650 Field Programmable Logic Devices

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN1600) Lecture 21: Dynamic Combinational Circuit Design Prof. Sherief Reda Division of.

Chapter 09 Advanced Techniques in CMOS Logic Circuits

S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN01600) Lecture 19: Combinational Circuit Design (1/3) Prof. Sherief Reda Division of Engineering,

Combinational circuits Lection 6

Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE VLSI Circuit Design Lecture 9 - Combinational.

Designing Combinational Logic Circuits: Part2 Alternative Logic Forms:

Lecture #24 Gates to circuits

S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN1600) Lecture 20: Combinational Circuit Design (2/3) Prof. Sherief Reda Division of Engineering,

Lecture #25 Timing issues

Introduction to CMOS VLSI Design Circuit Families.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 21: Differential Circuits and Sense Amplifiers Prof. Sherief Reda Division.

Circuit Families Adopted from David Harris of Harvey Mudd College.

Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 13 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Pseudo-nMOS, Dynamic CMOS and Domino.

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 1 Digital Integrated Circuits A Design Perspective Designing Combinational Logic Circuits.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 27: November 5, 2014 Dynamic Logic Midterm.

Digital CMOS Logic Circuits

S. RossEECS 40 Spring 2003 Lecture 24 Today we will Review charging of output capacitance (origin of gate delay) Calculate output capacitance Discuss fan-out.

Field-Effect Transistors 1.Understand MOSFET operation. 2. Understand the basic operation of CMOS logic gates. 3. Make use of p-fet and n-fet for logic.

1 Final Exam Review. 2 word7 is high if A2 A1 A0 = 111 word0 is high if A2 A1 A0 = 000 logical effort of each input is (1+3.5)/3 per wordline output.

Lecture 21, Slide 1EECS40, Fall 2004Prof. White Lecture #21 OUTLINE –Sequential logic circuits –Fan-out –Propagation delay –CMOS power consumption Reading:

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 18: Static Combinational Circuit Design (2/2) Prof. Sherief Reda Division.

VLSI Digital Systems Design Alternatives to Fully-Complementary CMOS Logic.

1 EE 587 SoC Design & Test Partha Pande School of EECS Washington State University

Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 10.1 EE4800 CMOS Digital IC Design & Analysis Lecture 10 Combinational Circuit Design Zhuo Feng.

1 EE 587 SoC Design & Test Partha Pande School of EECS Washington State University

CSET 4650 Field Programmable Logic Devices

1 Delay Estimation Most digital designs have multiple data paths some of which are not critical. The critical path is defined as the path the offers the.

MOS Transistors The gate material of Metal Oxide Semiconductor Field Effect Transistors was original made of metal hence the name. Present day devices’

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. C H A P T E R 14 Advanced MOS and Bipolar Logic Circuits.

EE415 VLSI Design DYNAMIC LOGIC [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

A Class Presentation for VLSI Course by : Fatemeh Refan Based on the work Leakage Power Analysis and Comparison of Deep Submicron Logic Gates Geoff Merrett.

EE 447 VLSI Design Lecture 8: Circuit Families.

CMOS DYNAMIC LOGIC DESIGN

Chapter 1 Combinational CMOS Logic Circuits Lecture # 4 Pass Transistors and Transmission Gates.

3. Logic Gate 3.1 Introduction static, fully complementary CMOS psudo-nMOS, domino logic 3.2 Combinational Logic Functions combinational logic ---- specification.

ECE442: Digital ElectronicsSpring 2008, CSUN, Zahid Static CMOS Logic ECE442: Digital Electronics.

1 Clockless Computing Montek Singh Thu, Sep 6, 2007  Review: Logic Gate Families  A classic asynchronous pipeline by Williams.

Lecture 10: Circuit Families. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 10: Circuit Families2 Outline  Pseudo-nMOS Logic  Dynamic Logic  Pass Transistor.

Linear Delay Model In general the propagation delay of a gate can be written as: d = f + p –p is the delay due to intrinsic capacitance. –f is the effort.

CSE477 L07 Pass Transistor Logic.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 07: Pass Transistor Logic Mary Jane Irwin (

Advanced VLSI Design Unit 04: Combinational and Sequential Circuits.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 22: November 1, 2010 Dynamic Logic.

Introduction to CMOS VLSI Design Lecture 9: Circuit Families

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Properties of Complementary CMOS Gates.

Solid-State Devices & Circuits

Static CMOS Logic Seating chart updates

EE141 © Digital Integrated Circuits 2nd Combinational Circuits 1 A few notes for your design  Finger and multiplier in schematic design  Parametric analysis.

CMOS Logic Gates. NMOS transistor acts as a switch 2 When gate voltage is 0 V No channel is formed current does not flow easily “open switch” When gate.

EE415 VLSI Design. Read 4.1, 4.2 COMBINATIONAL LOGIC.

1 Dynamic CMOS Chapter 9 of Textbook. 2 Dynamic CMOS  In static circuits at every point in time (except when switching) the output is connected to either.

EE141 Combinational Circuits 1 Chapter 6 (I) Designing Combinational Logic Circuits Dynamic CMOS LogicDynamic CMOS Logic V1.0 5/4/2003.

Static Logic vs. Pseudo-nMOS Static Logic includes pull-up and pull-down networks - 2n transistors for n-input function. Pseudo-nMOS - n+1 transistors.

EE 466/586 VLSI Design Partha Pande School of EECS Washington State University

1 Recap: Lecture 4 Logic Implementation Styles:  Static CMOS logic  Dynamic logic, or “domino” logic  Transmission gates, or “pass-transistor” logic.

CMOS LOGIC STRUCTURE. 1.CMOS COMPLEMENTARY LOGIC CMOS is a tech. for constructing IC. CMOS referred to as Complementary Symmetry MOS(COS-MOS) Reason:

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Design Technologies.

1 Clockless Logic Montek Singh Thu, Mar 2, Review: Logic Gate Families  Static CMOS logic  Dynamic logic, or “domino” logic  Transmission gates,

Lecture 10: Circuit Families

Lecture 10: Circuit Families

Subject Name: Fundamentals Of CMOS VLSI Subject Code: 10EC56

Day 21: October 29, 2010 Registers Dynamic Logic

Combinational Circuit Design

Lecture 10: Circuit Families

Presentation transcript:

Ratioed Circuits Ratioed circuits use weak pull-up and stronger pull-down networks. The input capacitance is reduced and hence logical effort. Correct operation depends on correct pull-up and pull-down ratio. Ratioed circuits dissipate static power and must be used sparingly. The pull-up network for ratioed CMOS (pseudo-nMOS) uses a single pMOS whose gate terminal is grounded (device is always on). To compute the logical effort of the pseudo-nMOS gates we use the full complementary CMOS inverter as reference. Assume that the full complementary CMOS inverter delivers current I in both rising and falling transition and that a properly sized pMOS device in a pseudo-NMOS circuit has its width ½ that of the nMOS pull-down network. The logical effort is given by the ratio of the pseudo-nMOS inverter input capacitance to that of the unit CMOS inverter input capacitance.

Ratioed Circuits The objective is to have the nMOS pull-down network sized appropriately to effectively fight the pMOS device for correct output. The output current is therefore the difference between the pull-down current and the pull-up current. The parasitic delay p is determined by comparing the parasitic output capacitance of the pseudo-nMOS inverter to that of the unit sized inverter. A Pseudo-nMOS NAND can be shown to be generally slower than static CMOS, but pseudo-nMOS style shows improved delay for gates such as the NOR gate. Why? Ganged CMOS is widely known as Majority gate. A single configuration can perform different logic functions depending on input values.

Cascode Voltage Switch Cascode voltage switch logic (CVSL) eliminates the static power consumption of the pseudo-nMOS design style. It has a pair of nMOS pull-down networks to compute an output and its complementary value from associated input signals and their complementary values. The pull-down networks are complementary with one side having series transistors while the other has a parallel combination. CVSL has the potential to improve switching speed since the gate input capacitance is reduced.

Dynamic Circuits The drawbacks of ratioed logic include: Slow rising transitions Contention on the falling transitions Static power dissipation and Non-zero output low voltage Dynamic circuits require a precharge and evaluate phase and use a clock to circumvent the problems of the pseudo-nMOS approach. Dynamic circuits are fast because of lower input capacitance and no contention during switching. Dynamic circuits have zero static power dissipation?????? The clock and the associated logic consume considerable dynamic power. Dynamic circuits are sensitive to noise during evaluation.

Domino Logic Floating nodes could result when the input transitions from a HIGH to a LOW before the precharge signal is asserted. When this condition occurs both the nMOS pull-down network and the pMOS (precharge devices are OFF. Domino logic allows for the placement of static and dynamic circuits to eliminate floating nodes?????? Domino gates are non-inverting. Dual-rail domino logic gates encode each signal with a pair of wires. The output and input signal pairs are denoted with _h and _l to indicate their status (high or low). Inputs and their complementary values are accepted by dual rail domino. These gates have both a precharge and an evaluate clock.