5-1 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Principles of Computer Architecture Miles Murdocca and Vincent Heuring Chapter 5: Languages and the Machine

5-2 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Chapter Contents 5.1 The Compilation Process 5.2 The Assembly Process 5.3 Linking and Loading 5.4 Macros 5.5 Case Study: Extensions to the Instruction Set – The Intel MMX™ and Motorola AltiVec™ SIMD Instructions

5-3 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization The Compilation Process Compilation translates a program written in a high level language into a functionally equivalent program in assembly language. Consider a simple high-level language assignment statement: A = B + 4; Steps involved in compiling this statement into assemby code: — Reducing the program text to the basic symbols of the language (for example, into identifiers such as A and B), denotations such as the constant value 4, and program delimiters such as = and +. This portion of compilation is referred to as lexical analysis. — Parsing symbols to recognize the underlying program structure. For the statement above, the parser must recognize the form: Identifier “=” Expression, where Expression is further parsed into the form: Identifier “+” Constant. Parsing is sometimes called syntactic analysis.

5-4 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization The Compilation Process — Name analysis: associating the names A and B with particular program variables, and further associating them with particular memory locations where the variables are located at run time. — Type analysis: determining the types of all data items. In the example above, variables A and B and constant 4 would be recognized as being of type int in some languages. Name and type analysis are sometimes referred to together as semantic analysis: determining the underlying meaning of program components. — Action mapping and code generation: associating program statements with their appropriate assembly language sequence. In the statement above, the assembly language sequence might be as follows: ld [B], %r0, %r1! Get variable B into a register. add %r1, 4, %r2! Compute the value of the expression st %r2, %r0, [A]! Make the assignment.

5-5 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization The Assembly Process The process of translating an assembly language program into a machine language program is referred to as the assembly process. Production assemblers generally provide this support: — Allow programmer to specify locations of data and code. — Provide assembly-language mnemonics for all machine instructions and addressing modes, and translate valid assembly language statements into the equivalent machine language. — Permit symbolic labels to represent addresses and constants. — Provide a means for the programmer to specify the starting address of the program, if there is one; and provide a degree of assemble-time arithmetic. — Include a mechanism that allows variables to be defined in one assembly language program and used in another, separately assembled program. — Support macro expansion.

5-6 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Assembly Example We explore how the assembly process proceeds by “hand assembling” a simple ARC assembly language program.

5-7 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Instruc- tion For- mats and PSR Format for the ARC

5-8 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Assembled Code ld [x], %r ld [y], %r addcc %r1,%r2,%r st %r3, [z] jmpl %r15+4, %r

5-9 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Forward Referencing An example of forward referencing:

5-10 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization

5-11 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Assembled Program

5-12 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Linking: Using.global and.extern A.global is used in the module where a symbol is defined and a.extern is used in every other module that refers to it.

5-13 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Linking and Loading: Symbol Tables Symbol tables for the previous example:

5-14 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Example ARC Program

5-15 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Macro Definition A macro definition for push:

5-16 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Recursive Macro Expansion

5-17 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Intel MMX (MultiMedia eXtensions) Vector addition of eight bytes by the Intel PADDB mm0, mm1 instruction:

5-18 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Intel and Motorola Vector Registers Intel “aliases” the floating point registers as MMX registers. This means that the Pentium’s 8 64-bit floating-point registers do double- duty as MMX registers. Motorola implements bit vector registers as a new set, separate and distinct from the floating-point registers.

5-19 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization MMX and AltiVec Arithmetic Instructions

5-20 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Comparing Two MMX Byte Vectors for Equality

5-21 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Conditional Assignment of an MMX Byte Vector

5-22 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Addressing Modes Four ways of computing the address of a value in memory: (1) a constant value known at assembly time, (2) the contents of a register, (3) the sum of two registers, (4) the sum of a register and a constant. The table gives names to these and other addressing modes.

5-23 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Subroutine Linkage – Registers Subroutine linkage with registers passes parameters in registers.

5-24 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Subroutine Linkage – Data Link Area Subroutine linkage with a data link area passes parameters in a separate area in memory. The address of the memory area is passed in a register (%r5 here).

5-25 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Subroutine Linkage – Stack Subroutine linkage with a stack passes parameters on a stack.

5-26 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Stack Linkage Example A C program illustrates nested function calls.

5-27 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Stack Linkage Example (cont’) (a-f) Stack behavior during execution of the program shown in previous slide.

5-28 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Stack Linkage Example (cont’) (g-k) Stack behavior during execution of the C program shown previously.

5-29 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Input and Output for the ISA Memory map for the ARC, showing memory mapped I/O.

5-30 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Touchscreen I/O Device A user selecting an object on a touchscreen:

5-31 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Flowchart for I/O Device Flowchart illustrating the control structure of a program that tracks a touchscreen.

5-32 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Java Virtual Machine Architecture

5-33 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Java Pro- gram and Com- piled Class File

5-34 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization A Java Class File

5-35 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization A Java Class File (Cont’)

5-36 Chapter 5 - Languages and the Machine Department of Information Technology, Radford University ITEC 352 Computer Organization Byte Code for Java Program Disassembled byte code for previous Java program. LocationCodeMnemonicMeaning 0x00e30x10bipushPush next byte onto stack 0x00e40x0f15Argument to bipush 0x00e50x3cistore_1Pop stack to local variable 1 0x00e60x10bipushPush next byte onto stack 0x00e70x099Argument to bipush 0x00e80x3distore_2Pop stack to local variable 2 0x00e90x03iconst_0Push 0 onto stack 0x00ea0x3eistore_3Pop stack to local variable 3 0x00eb0x1biload_1Push local variable 1 onto stack 0x00ec0x1ciload_2Push local variable 2 onto stack 0x00ed0x60iaddAdd top two stack elements 0x00ee0x3eistore_3Pop stack to local variable 3 0x00ef0xb1returnReturn