George Mason University ECE 448 – FPGA and ASIC Design with VHDL Experiment 7 VHDL Modeling of Embedded Microprocessors and Microcontrollers

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Simple Microprocessor

3ECE 448 – FPGA and ASIC Design with VHDL Basic Architecture Control unit and datapath Note similarity to single-purpose processor Key differences Datapath is general Control unit doesn’t store the algorithm – the algorithm is “programmed” into the memory Processor Control unitDatapath ALU Registers IRPC Controller Memory I/O Control /Status Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"

4ECE 448 – FPGA and ASIC Design with VHDL Instruction Cycles Processor Control unitDatapath ALU Registers IRPC Controller Memory I/O Control /Status load R0, M[500] inc R1, R0 101 store M[501], R1 102 R0R1 PC= Fetch ops Exec. Store results clk Fetch load R0, M[500] Decode 100 Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"

5ECE 448 – FPGA and ASIC Design with VHDL Architectural Considerations Clock frequency Inverse of clock period Must be longer than longest register to register delay in entire processor Memory access is often the longest Processor Control unitDatapath ALU Registers IRPC Controller Memory I/O Control /Status Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"

6ECE 448 – FPGA and ASIC Design with VHDL A Simple (Trivial) Instruction Set opcode operands MOV Rn, direct Rm ADD Rn, Rm 0000Rndirect 0010Rn 0100RmRn Rn = M(direct) Rn = Rn + Rm SUB Rn, Rm 0101Rm Rn = Rn - Rm MOV Rn, #immed. 0011Rnimmediate Rn = immediate Assembly instruct.First byteSecond byteOperation JZ Rn, relative 0110Rnrelative PC = PC+ relative (only if Rn is 0) Rn MOV direct, Rn 0001Rndirect M(direct) = Rn Rm M(Rn) = Rm Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"

7ECE 448 – FPGA and ASIC Design with VHDL Addressing Modes Data Immediate Register-direct Register indirect Direct Indirect Data Operand field Register address Memory address Data Memory address Data Addressing mode Register-file contents Memory contents Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"

8ECE 448 – FPGA and ASIC Design with VHDL Sample Program int total = 0; for (int i=10; i!=0; i--) total += i; // next instructions... C program MOV R0, #0; // total = 0 MOV R1, #10; // i = 10 JZ R1, Next; // Done if i=0 ADD R0, R1; // total += i MOV R2, #1; // constant 1 JZ R3, Loop; // Jump always Loop: Next:// next instructions... SUB R1, R2; // i-- Equivalent assembly program MOV R3, #0; // constant Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"

9ECE 448 – FPGA and ASIC Design with VHDL Architecture of a Simple Microprocessor Storage devices for each declared variable register file holds each of the variables Functional units to carry out the FSMD operations One ALU carries out every required operation Connections added among the components’ ports corresponding to the operations required by the FSM Unique identifiers created for every control signal Datapath IRPC Controller (Next-state and control logic; state register) Memory RF (16) RFwa RFwe RFr1a RFr1e RFr2a RFr2e RFr1RFr2 RFw ALU ALUs 2x1 mux ALUz RFs PCld PCinc PCclr 3x1 mux Ms MweMre To all input control signals From all output control signals Control unit 16 Irld A D 1 0 Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"

10ECE 448 – FPGA and ASIC Design with VHDL A Simple Microprocessor FSM operations that replace the FSMD operations after a datapath is created RFwa=rn; RFwe=1; RFs=01; Ms=01; Mre=1; RFr1a=rn; RFr1e=1; Ms=01; Mwe=1; RFr1a=rn; RFr1e=1; Ms=00; Mwe=1; RFwa=rn; RFwe=1; RFs=10; RFwa=rn; RFwe=1; RFs=00; RFr1a=rn; RFr1e=1; RFr2a=rm; RFr2e=1; ALUs=00 RFwa=rn; RFwe=1; RFs=00; RFr1a=rn; RFr1e=1; RFr2a=rm; RFr2e=1; ALUs=01 PCld= ALUz; RFrla=rn; RFrle=1; MS=10; Irld=1; Mre=1; PCinc=1; PCclr=1; Reset Fetch Decode IR=M[PC]; PC=PC+1 Mov1 RF[rn] = M[dir] Mov2 Mov3 Mov4 Add Sub Jz op = 0000 M[dir] = RF[rn] M[rn] = RF[rm] RF[rn]= imm RF[rn] =RF[rn]+RF[rm] RF[rn] = RF[rn]-RF[rm] PC=(RF[rn]=0) ?rel :PC to Fetch PC=0; from states below FSMD Datapath IRPC Controller (Next-state and control logic; state register) Memory RF (16) RFwa RFwe RFr1a RFr1e RFr2a RFr2e RFr1RFr2 RFw ALU ALUs 2x1 mux ALUz RFs PCld PCinc PCclr 3x1 mux Ms MweMre To all input contro l signals From all output control signals Control unit 16 Irld A D 1 0 You just built a simple microprocessor! Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"

George Mason University ECE 448 – FPGA and ASIC Design with VHDL PIC Microcontroller

12ECE 448 – FPGA and ASIC Design with VHDL PIC Microcontroller implemented inside of an FPGA device PIC µController FPGA PORTB PORTA 7-Seg Decoder PORTA Display PORTC = PORTC(0)STROBE CLK RESET

13ECE 448 – FPGA and ASIC Design with VHDL PICROM 256 x 12 Data Addr PROGRAM PCPC Instruction Decoder W ALU COMPUTATIONS CONSTANTS OPCODES Address Bus Data Bus 8 8 CONTROL UNIT MCLRCLK EXTENDED ALU PORTAPORTBPORTC 488 DATA FSR DinDout REGFILE R8 R31 Fsel PIC Microcontroller Core

14ECE 448 – FPGA and ASIC Design with VHDL Set Port Directions RESET Sum <= ‘0’ Counter <= ‘0’ Wait for a rising edge at Port C(0) Port B <= Port A Sum <= Sum + Port A Counter <= Counter + 1 Counter = 8? N Y Wait for a rising edge at Port C(0) Port B <= Sum(3 downto 0) Wait for a rising edge at Port C(0) Port B <= Sum(7 downto 4) Flowchart of our PIC program

15ECE 448 – FPGA and ASIC Design with VHDL Selected Registers of PIC W PC PORTA ADDR Working Register (Accumulator) Program Counter PORTB PORTC R8 R9 R30 R31 1F Bidirectional Input/Output Ports Register File (General Purpose Registers) TRISA Direction Registers for Ports A, B & C TRISB TRISC      1E.... 0A R10

16ECE 448 – FPGA and ASIC Design with VHDL Selected PIC Instructions (1) MOVF f, d f W MOVF f, 0 MOVF f, 1 MOVWF f W f MOVLW k k W k  f 

17ECE 448 – FPGA and ASIC Design with VHDL Selected PIC Instructions (2) CLRF f f 0 CLRW W 0 f 

18ECE 448 – FPGA and ASIC Design with VHDL Selected PIC Instructions (3) INCF f, d f INCF f,1 +1 W INCF f,0

19ECE 448 – FPGA and ASIC Design with VHDL Selected PIC Instructions (4) ADDWF f, d W ADDWF f, 1 + f ADDWF f, 0

20ECE 448 – FPGA and ASIC Design with VHDL Selected PIC Instructions (5) ANDWF f, d W ANDWF f, 1 and f ANDWF f, 0

21ECE 448 – FPGA and ASIC Design with VHDL Selected PIC Instructions (6) SWAPF f, d SWAPF f, 0 f H f L W SWAPF f, 1

22ECE 448 – FPGA and ASIC Design with VHDL Selected PIC Instructions (7) CALL label label RETLW CALL label label GOTO label label

23ECE 448 – FPGA and ASIC Design with VHDL Selected PIC Instructions (8) BTFSC f, b b 7 0 f f(b) = 0? BTFSC f, b Yes No After-next Instruction Next instruction

24ECE 448 – FPGA and ASIC Design with VHDL Selected PIC Instructions (8) BTFSS f, b b 7 0 f f(b) = 1? BTFSS f, b Yes No After-next Instruction Next instruction

25ECE 448 – FPGA and ASIC Design with VHDL Selected PIC Instructions (9) TRIS f TRISB 8 TRISA 4 TRISC 8 W TRIS PORTA TRIS PORTB TRIS PORTC 1 – Input port bit direction 0 – Output port bit direction

26ECE 448 – FPGA and ASIC Design with VHDL MPASM *.ASM *.LST*.HEX MPSIM Source File in the PIC Assembly Language Listing FileHEX File PIC Programming Environment

27ECE 448 – FPGA and ASIC Design with VHDL Questions?