Eric Allender Rutgers University Dual VP Classes Joint work with Anna Gál (U. Texas) and Ian Mertz (Rutgers) MFCS, Milan, August 27, 2015

Eric Allender: Dual VP Classes < 2 >< 2 > Our Contributions  New characterizations of ACC 1 and TC 1.  New examples of fan-in reduction.  Highlight connections between ACC 1 and VP.  Revisit the Immerman-Landau Conjecture, and offer some new conjectures about circuit complexity classes.  But first …let’s review the relevant complexity classes.

Eric Allender: Dual VP Classes < 3 >< 3 > NP P AC 1 NL L NC 1 AC 0 Log-Depth Poly-size Fan-in 2 Unbounded Fan-in Fan-in is Important!

Eric Allender: Dual VP Classes < 4 >< 4 > NP P AC 1 SAC 1 =LogCFL NL L NC 1 AC 0 Log-Depth Poly-size Fan-in is Important! Semi-unbounded fan-in Λ fan-in 2 V fan-in n k

Eric Allender: Dual VP Classes < 5 >< 5 > NP P TC 1 AC 1 SAC 1 =LogCFL NL L NC 1 TC 0 AC 0 Components are Important! Log depth O(1) depth Majority gates

Eric Allender: Dual VP Classes < 6 >< 6 > P #P NP P TC 1 AC 1 SAC 1 =LogCFL NL L NC 1 TC 0 AC 0 L #L = L Det(Q)

Eric Allender: Dual VP Classes < 7 >< 7 > P #P =P VNP(Q) NP P TC 1 AC 1 SAC 1 =LogCFL NL L NC 1 TC 0 AC 0 L #L = L Det(Q) L #LogCFL = L VP(Q)

Eric Allender: Dual VP Classes < 8 >< 8 > Valiant’s Class VP  VP(R) is the class of families (f n ) of multivariate polynomials over R such that – f n has degree n O(1). – There is a family of arithmetic circuits (C n ) of size poly(n) such that C n computes f n.  Furthermore, C n can be assumed to have depth O(log n) with fan-in 2 x and unbounded fan-in +. (Semiunbounded fan-in arithmetic circuits.)  #SAC 1 = the functions in VP(N).

Eric Allender: Dual VP Classes < 9 >< 9 > P #P =P VNP(Q) NP P TC 1 AC 1 SAC 1 =LogCFL NL L NC 1 TC 0 AC 0 L #L = L Det(Q) L #LogCFL = L VP(Q)

Eric Allender: Dual VP Classes P #P =P VNP(Q) NP P TC 1 AC 1 SAC 1 =LogCFL NL L #NC 1 (Q) NC 1 TC 0 AC 0 L #L = L Det(Q) L #LogCFL = L VP(Q) =L #SAC 1 # AC 1 (Q) Not contained in P for a trivial reason: The output has more than poly-many bits.

Eric Allender: Dual VP Classes P #P =P VNP(Q) NP P TC 1 AC 1 SAC 1 =LogCFL NL L #NC 1 (Q) NC 1 TC 0 AC 0 L #L = L Det(Q) L #LogCFL = L VP(Q) =L #SAC 1 = # AC 1 (F p n ) ≈ # NC 1 (F p n ) L VP(F p n ) = The meaning of F p n is: Circuit C n is interpreted modulo the n th prime. = # AC 0 (F p n ) ≈ # AC 0 (Q)

Eric Allender: Dual VP Classes P #P =P VNP(Q) NP P TC 1 ACC 1 AC 1 SAC 1 =LogCFL NL L #NC 1 (Q) NC 1 TC 0 ACC 0 AC 0 L #L = L Det(Q) L #LogCFL = L VP(Q) =L #SAC 1 = # AC 1 (F p n ) L VP(F p n ) = ACC i = U m AC i [m] = U q # AC 0 (F q ) = U q # AC 1 (F q )

Eric Allender: Dual VP Classes P #P =P VNP(Q) NP P TC 1 ACC 1 AC 1 SAC 1 =LogCFL NL L #NC 1 (Q) NC 1 TC 0 ACC 0 AC 0 L #L = L Det(Q) L #LogCFL = L VP(Q) =L #SAC 1 = # AC 1 (F p n ) L VP(F p n ) = Our focus lies here.

Eric Allender: Dual VP Classes Dual VP Classes VP(R): Unbounded + Bounded x SAC 1 =LogCFL = VP(B 2 ): Unbounded V Bounded Λ But LogCFL is closed under complement! [BCDRT]

Eric Allender: Dual VP Classes Dual VP Classes VP(R): Unbounded + Bounded x SAC 1 =LogCFL = VP(B 2 ): Unbounded V Bounded Λ = Unbounded Λ Bounded V

Eric Allender: Dual VP Classes Dual VP Classes VP(R): Unbounded + Bounded x SAC 1 =LogCFL = VP(B 2 ): Unbounded V Bounded Λ = ΛP(B 2 ): Unbounded Λ Bounded V ΛP(R): Unbounded x Bounded + Is this interesting??

Eric Allender: Dual VP Classes New Characterizations of ACC 1  ACC 1 = U q #AC 1 (F q )  = U q ΛP(F q )  Fan-in Reduction (from unbounded to semiunbounded)  #AC 1 (F q ) = AC 1 [q(q-1)]  ΛP(F q ) = AC 1 [q-1]

Eric Allender: Dual VP Classes …and TC 1  ACC 1 = U q #AC 1 (F q )  = U q ΛP(F q )  Fan-in Reduction (from unbounded to semiunbounded)  #AC 1 (F q ) = AC 1 [q(q-1)]  ΛP(F q ) = AC 1 [q-1]  TC 1 = # AC 1 (F p n ) = L ΛP(F p n )

Eric Allender: Dual VP Classes Boolean Fan-In Reduction  By definition, AC 1 [m] has poly size, log depth, with unbounded fan-in MOD m, V and Λ gates.  Theorem: The fan-in of the V and Λ gates can be reduced to log n, with no loss of computational power. – In symbols: AC 1 [m] = log-AC 1 [m].  Theorem: If m is not a prime power, then the fan-in can be reduced to 2, with no loss of power. AC 1 [m] = 2-AC 1 [m].  …and to ZERO! AC 1 [m] = 0-AC 1 [m].

Eric Allender: Dual VP Classes ACC 1 and VP  That is: ACC 1 corresponds to uniform families of MOD m gates (with no other hardware).  Compare the circuit characterization of ACC 1 with the circuit characterization of VP(F q ): – For any odd prime q, VP(F q ) is the class of languages accepted by uniform families of MOD q gates (with no other hardware).

Eric Allender: Dual VP Classes ACC 1 and VP  That is: ACC 1 corresponds to uniform families of MOD m gates (with no other hardware).  Compare the circuit characterization of ACC 1 with the circuit characterization of VP(F q ): – For any odd prime q, VP(F q ) is the class of languages accepted by uniform families of MOD q gates (with no other hardware).  Thus, over finite fields, the difference between VP and ΛP (=ACC 1 ) boils down to the difference between primes and composites.

Eric Allender: Dual VP Classes Degree Reduction  We have seen examples of fan-in reduction for Boolean circuits (such as AC 1 [5] = log-AC 1 [5]).  And we have seen examples of fan-in reduction for arithmetic circuits (such as U q #AC 1 (F q ) = U q ΛP(F q ))…  …which only reduced the fan-in of + gates – and hence did not result in a reduction of the degree of the polynomial represented.  Should we expect any reduction of the fan-in of x gates to be possible?

Eric Allender: Dual VP Classes Degree Reduction  Should we expect any reduction of the fan-in of x gates to be possible?  Consider the Immerman-Landau conjecture: – TC 1 = L Det(Q) – Equivalently: # AC 1 (F p n ) = L Det(Q) = L VP(Q) = L VP(F p n )  [Buhrman et al] argued that it would be unlikely for a high-degree arithmetic class to coincide with a polynomial-degree arithmetic class.

Eric Allender: Dual VP Classes Degree Reduction  We present examples where degree reduction is possible.  Define #WSAC 1 to be circuits with a “weak” form of the semiunbounded fan-in restriction: poly-size, log depth circuits with unbounded fan-in + gates, and logarithmic-fan-in x gates.  Theorem: For any prime q, AC 1 [q] = #WSAC 1 (F q ).  Corollary: #AC 1 (F 2 ) = #WSAC 1 (F 2 ).

Eric Allender: Dual VP Classes Degree Reduction  Consider #AC 1 (F 2 ) = #WSAC 1 (F 2 ).  Polynomials in #AC 1 (F 2 ) have degree n O(log n).  Polynomials in #WSAC 1 (F 2 ) have degree n O(log log n).  This is proved using off-the-shelf techniques (isolation lemma, derandomization using walks on expanders). We see no reason why degree n O(log log n) should be optimal.  If it can be reduced to n O(1), then #AC 1 (F 2 ) = VP(F 2 ).

Eric Allender: Dual VP Classes Degree Reduction  Consider #AC 1 (F 2 ) = #WSAC 1 (F 2 ).  Polynomials in #AC 1 (F 2 ) have degree n O(log n).  Polynomials in #WSAC 1 (F 2 ) have degree n O(log log n).  This is proved using off-the-shelf techniques (isolation lemma, derandomization using walks on expanders). We see no reason why degree n O(log log n) should be optimal.  If it can be reduced to n O(1), then #AC 1 (F 2 ) = VP(F 2 ) = ΛP(F 3 ).

Eric Allender: Dual VP Classes Open Questions  We believe that the arguments presented against the Immerman-Landau conjecture – which are based on degree-reduction being unlikely – are weakened by examples of degree-reduction. Can one improve the degree reduction?  Can the connection between ACC 1 and VP be strengthened?  Is U m L VP(Z m ) equal to U m AC 1 [m] (= ACC 1 )?  This would imply AC 1 is contained in L VP[Z m ] for some m.

Eric Allender: Dual VP Classes Open Questions  We believe that the arguments presented against the Immerman-Landau conjecture – which are based on degree-reduction being unlikely – are weakened by examples of degree-reduction. Can one improve the degree reduction?  Can the connection between ACC 1 and VP be strengthened?  Is U m L VP(Z m ) equal to U m AC 1 [m] (= ACC 1 )?  This would imply AC 1 is contained in L VP[Z m ] for some m. (SAC 1 is there, nonuniformly.)

Eric Allender: Dual VP Classes Thank you!

Eric Allender: Dual VP Classes #P NP P TC 1 ACC 1 AC 1 SAC 1 =LogCFL NL L #NC 1 NC 1 TC 0 ACC 0 AC 0