Complementary CMOS Logic Style Construction (cont.) Digital Integrated Circuits© Prentice Hall 1995 Introduction

Example Gate: NAND Digital Integrated Circuits© Prentice Hall 1995 Introduction

Example Gate: NOR Digital Integrated Circuits© Prentice Hall 1995 Introduction

Example Gate: COMPLEX CMOS GATE Digital Integrated Circuits© Prentice Hall 1995 Introduction

4-input NAND Gate In1In2In3In4 Vdd GND Out Digital Integrated Circuits© Prentice Hall 1995 Introduction

Properties of Complementary CMOS Gates Digital Integrated Circuits© Prentice Hall 1995 Introduction

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Complex Gate Structures A C B A B C Vdd Gnd Out Out = A+(B*C)... A B C And-Or-Invert (AOI) How to add terms?

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction OAI/AOI Duality A C B A B C Vdd Gnd Out Out = A*(B+C)... A B C Or-And-Invert (OAI) Out = A+(B*C)... Switch from: To: Demorgan’s Law in Action

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Demorgan’s Law in Action Out = A*(B+C)... A B C Or-And-Invert (OAI) A C B A B C Vdd Gnd Out

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Demorgan’s Law in Action Out = A*(B+C)... A B C Or-And-Invert (OAI) A C B A B C Vdd Gnd Out What is the Magic command to do this?

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Step by Step Layout of XNOR Gate –The equation for XNOR is: l f = (a * b) + (a' * b') –using DeMorgan's law on each of the two terms gives: l f = (a'+ b')' + (a + b)' –using DeMorgan's law on the two terms together gives: l f = ((a'+ b') * (a + b))' –This could be directly implemented with a single complementary CMOS gate: the equation is in a simple negated product of sums form. This form can be implemented with the standard Or-And-Invert (OAI) style gate.

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Non-Inverted Inputs –However, using DeMorgan's law one more time on the left term gives: l f = ((a * b)' * (a + b))’ –This form uses no inverted inputs and can be implemented with two gates a NAND gate and an OAI gate. a b f

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Now lets lay it out l Start with Vdd! and GND! power buses. l Without any more information, about the use of this cell, make the power and ground lines in metal 1 l sized 3 and 3 apart. l Use poly as inputs A B and guess that C might be used.

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Step by Step l Now put in a stripe of N diffusion (green) creating a series of 2 n-channel transistors for the pull down structure for the first NAND gate. l Also put in a stripe of P diffusion (brown) and center connection to Vdd to plan for a parallel connection for the pull up structure for the NAND gate.

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction By step l Now finish wiring up the NAND gate. l Strap the two ends of the pull-up parallel transistors and tie them to the series pull down. l Use the polly line, C to tie them together.

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Or Gate l Begin to add the OR structure for the OAI gate above the NAND gate transistors. l This allows us to share the poly lines for A and B inputs. l Since we are building an OR structure, its series in the pull up and parallel in the pull down.

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction 1-Bit Full Adder l Sum = A xor B xor C l Cout = AB + AC + BC expand sum Sum = ABC+AB’C’+A’BC’+A’B’C (exactly 1 or 3 inputs true) use Cout to help generate Sum l Sum = ABC + Cout’(A+B+Cin)

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Full Adder (4 gates)

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Full Adder (4 gates)