Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 3: September 3, 2014 Gates from Transistors

Previously Simplified models for reasoning about transistor circuits –Zeroth-order Penn ESE370 Fall DeHon 2

Today How to construct static CMOS gates Penn ESE370 Fall DeHon 3

Outline Circuit understanding (preclass) –Gate function identification Static CMOS –Structure –Inverter –Construct gate –Inverting –Cascading Penn ESE370 Fall DeHon 4

Why Zeroth Order Useful? Allows us to reason (mostly) at logic level about steady-state functionality of typical gate circuits Make sure understand logical function (achieve logical function) before worrying about performance details Penn ESE370 Fall DeHon 5

What gate? Penn ESE370 Fall DeHon 6

What function? Penn ESE370 Fall DeHon 7

DeMorgan’s Law /f = a + b What is f? Penn ESE370 Fall DeHon 8

What function? Penn ESE370 Fall DeHon 9

Static CMOS Gate Penn ESE370 Fall DeHon 10

Static CMOS Gate Structure Penn ESE370 Fall DeHon 11

Static CMOS Gate Structure Penn ESE370 Fall DeHon 12

Static CMOS Gate Structure Drives rail-to-rail –Power rails are Vdd and Gnd –output is Vdd or Gnd Inputs connects to gates  load is capacitive Once charge capacitive output, doesn’t use energy –(first order) Output actively driven Penn ESE370 Fall DeHon 13

Inverter Out = /in Penn ESE370 Fall DeHon 14

Inverter Penn ESE370 Fall DeHon 15

Why zeroth-order adequate? Static analysis – can ignore capacitors Capacitive loads – resistances don’t matter Feed forward for gates – –don’t generally have loops –can work forward from known values Logic drive to ground or Vdd (rail-to-rail) –Don’t have to reason about intermediate voltage levels Penn ESE370 Fall DeHon 16

What zeroth-order not tell us? Delay Dynamics Behavior if not –Capacitively loaded –Acyclic (if there are Loops) –Rail-to-rail drive (voltages between 0 and Vdd) Penn ESE370 Fall DeHon 17

Gate Design Example Penn ESE370 Fall DeHon 18

Gate Design Design gate to perform: f=(/a+/b)*/c Penn ESE370 Fall DeHon 19

f=(/a+/b)*/c Strategy: 1.Use static CMOS structure 2.Design PMOS pullup for f 3.Use DeMorgan’s Law to determine /f 4.Design NMOS pulldown for /f Penn ESE370 Fall DeHon 20

f=(/a+/b)*/c PMOS Pullup for f? Penn ESE370 Fall DeHon 21

f=(/a+/b)*/c Use DeMorgan’s Law to determine /f. What is /f ? Penn ESE370 Fall DeHon 22

f=(/a+/b)*/c NMOS Pulldown for /f? Penn ESE370 Fall DeHon 23

f=(/a+/b)*/c Penn ESE370 Fall DeHon 24 a c b

Static CMOS Source/Drains With PMOS on top, NMOS on bottom –PMOS source always at top (near Vdd) –NMOS source always at bottom (near Gnd) Penn ESE370 Fall DeHon 25

TA Office Hours M, W Poll for times Monday 5-9pm Poll for times Wednesday 5-9pm Penn ESE370 Fall DeHon 26

Inverting Gate Penn ESE370 Fall DeHon 27

Inverting Stage Each stage of Static CMOS gate is inverting Penn ESE370 Fall DeHon 28

How do we buffer? Penn ESE370 Fall DeHon 29

How implement OR? Penn ESE370 Fall DeHon 30

Cascading Stages Penn ESE370 Fall DeHon 31

Stages Can always cascade “stages” to build more complex gates Could simply build nor2 at circuit level and assemble arbitrary logic by combining – universality –but may not be smallest/fastest/least power Penn ESE370 Fall DeHon 32

Implement: f=a*/b Pullup? Pulldown? Penn ESE370 Fall DeHon 33

f=a*/b Penn ESE370 Fall DeHon 34

Course Alum – IBM Jobs Brian Yavoich – VLSI SRAM circuit design at IBM –Took this course Fall 2011 –Advertising full-time and summer hardware jobs at IBM Penn ESE370 Fall DeHon 35

Big Idea Systematic construction of any gate from transistors 1.Use static CMOS structure 2.Design PMOS pullup for f 3.Use DeMorgan’s Law to determine /f 4.Design NMOS pulldown for /f Penn ESE370 Fall DeHon 36

Admin Office hours –Ron (TA): Monday and Wednesday, Ketterer –Tuesday: Andre 4:15-5:30pm Levine 270 Thursday: HW1 due identify gates; use electric Friday in Detkin (RCA) Lab –Please read through HW2, Lab1 details –Bring USB drive with you to lab on Friday to store waveforms Penn ESE370 Fall DeHon 37