Teaching VLSI Design Considering Future Industrial Requirements Matthias Hanke

Outline 1.Introduction 2.Lecture 3.Tutorial 4.Lab 5.Conclusion 1

Industrial Requirements Theoretical knowledge  Semiconductor physics  Wire lenght‘s signal influence  Circuit design  Synthesis mechanisms Practical experience  Hardware description  Electronic design automation (EDA) tools Theory Practice 2

Course Concept Professorship sponsored by Intel Education Initiative LectureTutorialLaboratory (2 s/w)(1 s/w)(3 s/w) 3 Theory Basic knowledge Practice Calculations Practice Tools

Lecture Overview Teaches the theoretical basics 2 sessions per week Manufacturing cost aspects Semiconductor materials and devices MOS Transistor physics and structure Wire delays Manufacturing process CMOS inverter and gates Design methodologies Reconfigurable devices Test and self-test methods 4

Tutorial Overview Offers exercises to theoretical topics from the lecture Practical problems motivate participants 1 session per week 5

Silicon Calculation of chip yield and cost Construction of the transistor plot 6 I DS V DS V GS -V T V DS < V GS - V T V DS > V GS - V T

Logic Logic equations, transistor-level schematics and stick diagrams Modeling wires by Elmore Delay Logical effort notation for path and gates 7 V DD V SS output A B C D A BCD nor4 V DD V SS ABCD 123 output nmos pmos

Laboratory Overview Teaches the handling of tools 3 sessions a week Goes through the complete design process from RTL to GDSII 8 RTL Simulation Gate-Level Simulation Post-Layout Simulation VHDL code Synthesis Place & Route

VHDL Core VHDL introductory session Identification of MIPS instructions in a given VHDL core Extend 16 Bit core to 32 Bit 9 PC Memory Data Register Memory Data Register Sign- Extend ALUOut A A B B MUX 0 1 Instruction + Data Memory Write Data Address Mem Data Instruction Register Instruction [20-16] Instruction [15-0] Instruction [25-21] MUX Register File Read Register 1 Read Register 2 Write Register Write Data Read Data 1 Read Data 2 Shift Left 2 MUX ALU Zero ALU Result MUX 0 1 Instruction [15-11] Instruction [15-0] 16 Bit32 Bit 4

Running Programs 10 Verify extended processor‘s behaviour by wave forms created by given binary program Create additional instruction and write own binary program Compile assembly code to create binary programs

Gate Level Gate Level Synthesis for 90nm Compare 90nm design maximum frequency to 60 and 45nm Gate level delay sensitive simulation Energy consumtion analysis Scanchain insertion and automatic test pattern generation Place and route 11 LibraryFrequency 90nm450 MHz 60nm700 MHz 45nm1.000 MHz

Conclusion We meet industrial demands Theory of lecture is consolidated by practice in tutorial and lab High practice share motivates students Course teaches the complete design process 12

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