1 Read out & data analysis of the MVD demonstrator S. Amar-Youcef, M. Deveaux, I. Fröhlich, J. Michel, C. Müntz, C. Schrader, S. Seddiki, T. Tischler, and J. Stroth

13th CBM Collaboration Meeting 2 Outline Goals Read out & data analysis software First measurements  Test of data consistency  Quality of the analog readout chain Summary

13th CBM Collaboration Meeting 3 Goals of the software Validation of the demonstrator Build C++ platform to test data sparsification algorithms and to compare with FPGA- implementation. Interfacing the demonstrator with CBM-Root and the Strasbourg pixel telescope Option to interface this algorithm with the CBMRoot digitizer to test it in simulation

13th CBM Collaboration Meeting 4 Data acquisition & Demonstrator Analysis Software (DAS) MIMOSA - chip HDD AD conversion Raw data transfer (Mode 0) Reader Reader + Offline data sparsification Analog/Digital cluster finder Strasbourg pixel beam telescope Reader Digitizer data sparsification GEANT+ MVD Digitizer Dedicated analysis, validation, radhardness, … CBMRoot interface MVD-clusters or MVD-hits FPGA data sparsification (Mode 1) HDD

13th CBM Collaboration Meeting 5 HDD Status MIMOSA - chip AD conversion Raw data transfer (Mode 0) Reader + Offline data sparsification Analog/Digital cluster finder Dedicated analysis, validation, radhardness, … Reader Strasbourg pixel beam telescope Reader Digitizer data sparsification GEANT+ MVD Digitizer CBMRoot interface MVD-clusters or MVD-hits FPGA data sparsification (Mode 1) HDD Analog cluster finder

13th CBM Collaboration Meeting 6 First usecase of the DAS Validation of analog readout chain of the demonstrator Demo-AUX analogue output sync. signals data transfer: OP-link monitoring MAPS add-on board Trb2 (TRBnet)‏ File Server data transfer: I/O-card or Test-setup Mi20 board (Previously tested with Strasbourg reference system)

13th CBM Collaboration Meeting 7 Test of data consistency Constant pixel sequence in frames, Since data is rearranged Any shift in pixel order reflect the dynamic range! If correctly arranged: CDS eliminates the dynamic range. Frame 0 Frame 1 Signal (ADC units) row column

13th CBM Collaboration Meeting 8 Tested for several 1000 consecutive frames => OK Performing CDS Frame 0Frame 1 CDS row column Signal (ADC units)

13th CBM Collaboration Meeting 9 Test of data consistency Hit distribution reproduces illumination spot by 55 Fe- source Order of pixels seems to be OK! Picture of the collimator of the Fe55-source

13th CBM Collaboration Meeting 10 Quality of the analog readout chain Significant parameters  Particle detection ability  Gain  Noise

13th CBM Collaboration Meeting 11 Particle detection ability Cluster-building for charge spectrum ( 55 Fe-source) 1. Significant hits (amplitude > 5*noise) → seed candidate 2. Test seed candidates: no adjacent pixel with larger amplitude 3. Seed found: take all adjacent pixels to build cluster Margin Hits Diode Hits As expected from reference system => OK CDS-Signal (ADC) Entries Hit-Cluster

13th CBM Collaboration Meeting 12 Gain test Using photons from 55 Fe-source for ADC calibration Gain = 6e/ADC Small, irrelevant variation with respect to reference system (Expected K-Peaks at 400ADC) => OK Margin Hits KαKα KβKβ CDS-Signal (ADC) Entries

13th CBM Collaboration Meeting 13 Noise measurement Noise: RMS of the fluctuations of the pixels over time F0-F1 RMS of Individual pixels Mean noise = 33e => Expected 25e Origin of additional noise was identified (preliminary analog cable). Building an dedicated cable is in progress, expect results within two weeks. row column Signal (ADC units)

13th CBM Collaboration Meeting 14 Summary The Demonstrator Analysis Software (DAS) is a software to analyse the data of the MVD-demonstrator within CBMRoot. It will allow to test the same data sparsification algorithms with real data and simulated data. It will interface the MVD + the Strasbourg pixel telescope with CBMRoot DAS was used to validate the FPGA-board of the MVD- demonstrator using a tested MIMOSA-20 chip. The data consistency of the FPGA-board was confirmed. The hit finding ability of the FPGA-board was confirmed. The source of a small additional noise with respect to the slower reference system was identified and will be fixed within the next weeks. The tests performed confirm the validity of the design of the FPGA-Board