Front-end Electronics for the Alice Detector Kjetil Ullaland Department of Physics and Technology, University of Bergen, Norway NFR meeting, University of Bergen

The ALICE Experiment

Time Projection Chamber Main tracking detector Provides particle id and momentum Detection of charged particles by ionization of the gas volume 2-dimensional read-out at end-caps, drift time gives 3rd coordinate 2 x 18 sectors 4356 Front-End Cards, serving roughly channels simulated low multiplicity event designed for dN ch /dy = 8000 : ~ tracks

36 TPC Sectors, served by 6 readout subsystems, Readout Control Unit (RCU) in total 216 RCUs and 4356 Front-End Cards Ethernet ( 1 MB/s ) Detector Data Link ( 200 MB / s ) COUNTING ROOM ALTRO bus ( 200 MB / s ) ON DETECTOR FEC 128 ch FEC 128 ch FEC 128 ch FEC 128 ch FEC 128 ch FEC 128 ch DETECTOR TTC optical Link (Clock, L1 and L2 ) RCU DCS board SIU interface Trigger interface ALTRO Bus Interface Monitoring and Safety Module Data assembler Branch A Branch B Data Acquisition Incl. HLT-RORC Detector Control System Trigger and Clock System Local Slow- Control (I 2 C-serial link) TPC Front-end Electronics

Readout Control Unit Consists of: –the RCU motherboard –a DCS (Detector Control System) board embedded computer –a SIU (Source Interface Unit) mezzanine card. The system makes use of SRAM based FPGAs. –Flexibility & options for reconfiguration Major concerns are –Radiation tolerance of the electronics. –The huge data rate of the system (up to 710 GB/s without zero-suppression). Low-level data rate lowered by: –A trigger based system. (Only read out data when there are valid data) –Compressing algorithms on the ALTRO chip on the Front End Card.

Readout Control Unit SIU DCSRCU

Readout Control Unit

In ALICE, complete RCUs are to be used in: – TPC sub-detector – PHOS sub-detector – FMD sub-detector – EMCAL sub-detector DCS board used in ALICE TRD sub-detector as well. Other experiments have also expressed an interest to use the RCU. Readout Control Unit

Detector Control System (216 RCUs with DCS Boards) (PC’s with communication software) (PC’s with graphical user interface) Supervisory Layer Control Layer Field Layer Front-End Device Interface (FED) Front-End Electronics Interface (FEE)

DCS Board Embedded Computer Single board computer used in several detectors in ALICE Combines LINUX operating system with a Programmable Logic Device (PLD) Device drivers introduces an abstraction layer, decoupling software from hardware. The conceptual design is a co-development between Bergen and Heidelberg. Final hardware designed and produced in Heidelberg. Firmware/software co-designed by Bergen and Heidelberg

RCU Motherboard RCU motherboard: –Prototype developed by Bergen. –Final version a co-development between Bergen and CERN. Mass production ongoing now! –Firmware is a co-development between Bergen and CERN RCU motherboard is in the data readout chain in the TPC detector. RCU motherboard host basic controlling functionalities for the FECs Irradiation tolerance is critical!

Radiation Effects Single Event Effects (SEE) –Single Event Latch-up (SEL) –Single Event Upset (SEU) –Single Event Functional Interrupt (SEFI) Cumulative Effects –Total ionizing dose (TID) –Displacement damage SEE : Single event effects are radiation induced errors due to a single charged particle depositing energy through ionization of the material. Si p

Programmable Devices FPGA: Field Programmable Gate Array –Introduced in 1985 by Xilinx, Inc. –Array of programmable logic blocks –Logic gates, LUTs, flip-flops etc SRAM based Configuration Memory –Controls behaviour of the logic blocks –SEE major concern –Sensitive to ionizing particles –Configuration memory may change content: 1  0 / 0  1 Flash based Configuration Memory –Cumulative effects is a concern

Simulations of Radiation Enviroment Main particles of concern are hadrons of energy above MeV (nuclear interactions) Total dose for 10 Alice years is 5.7 Gy or ~0.6kRad Expected hadron flux ~ 800 hadrons/cm 2 -s (worst case) Peak at MeV (Morsch, Sandoval, Tsiledakis GSI)

Irradiation Tests at TSL and OCL SRAM based FPGAs: –Xilinx Virtex-II Pro 7 (RCU) –Altera APEX20K (RCU old prototype) –Altera EPXA1-ARM (DCS card) FLASH based FPGAs: –Actel ProAsic APA075 (RCU) Integration test –DCS embedded computer –Full FEE readout Chain Discrete components Proton irradiation –Energy: ~29, 38 & 180 MeV –Flux [p/cm 2 /s] Neutron irradiation –Energy: 50, 95, 180 MeV –Flux: 10 3 – 10 4 [n/cm 2 /s]

Results Actel FPGA: Survived dose of ~ 7 kRad. Expected for ALICE: ~ 0.6 kRad 180 MeV) Xilinx & Altera FPGA:

Conclusions of the Irradiation Tests SRAM based FPGAs: –Error rate at the limit of what can be tolerated –Radiation tolerant schemes –Detect SEUs instantaneously –Real-time read-back of configuration memory –Active partial reconfiguration (supported by Xilinx) –Error detection and correction techniques Actel FPGA (Flash): –Dose results satisfying –(exp: ~ 0.6 kRad, res: ~ 7 kRad)

Active reconfiguration Functionality of both DCS and RCU board can experience errors due to radiation effects in the FPGAs Simple reloading of configuration data causes downtime and is thus not applicable to RCU board (interruption of data-flow) -Active error detection and reconfiguration scheme using an FPGA capable of refreshing firmware w/o interrupting operation Active Partial Reconfiguration “scrubbing”

Preliminary test results with scrubbing SEFI test with Xilinx Virtex-II Pro FPGA Scrubbing started after ~200 s: Errors are corrected Continuously ~sec to “scrubb” full device Improved to ~ms seconds Bit Lines, RED = Errors Plain Shift Register (flux ~1.5*10 7 p/cm 2 -s) Test carried out by G. Tröger, KIP

HLT-RORC

The HLT-RORC is the low-level part of the High Level Trigger. Main purpose is to do online processing of the data incoming data. Found on each of the Front-end Processors on the HLT Computer Farm, receiving data directly from the RCU. A dual purpose co-processor is being implemented which alternatively can do: –Hough-transform of collected raw-data. –Cluster-finding Implemented with a Xilinx Virtex-4 FPGA and a PCI interface

HLT-RORC Developed by Bergen: –Firmware for the Clusterfinder –Conceptual Software for the Clusterfinder and the Hough-transform –DMA controller with interrupt handling –Prototype HLT-RORC PCI card for firmware/software development and testing Engineering prototype of HLT-RORC mezzanine card developed by KIP in Heidelberg.

Status Mass production of RCU motherboard and DCS board embedded computer has started. Firmware on RCU, both on the main FPGA and on the support FPGA soon ready as final engineering prototype. Firmware and Software on DCS board soon ready as final engineering prototype. HLT RORC engineering prototype finished. HLT RORC firmware/software is under development.

Outlook More irradiation tests of FEE are scheduled. –Discrete components –Integration tests Assembling of Front End Cards in the TPC end plates at CERN December 2005 – February Commissioning of TPC RCU system from February-August TPC Electronics will be installed in the ALICE pit September HLT RORC: Integrate existing firmware modules. To be fully operative by commissioning of ALICE detector in 2007.

Acknowledgements J. Alme, B. Pommeresche, M. Richter, S. Bablok, D. Larsen, B. H. Straume, O. Torheim, K. Ullaland, D. Röhrich –Department of Physics and Technology, University of Bergen, Norway K. Røed, H. Helstrup –Faculty of Engineering, Bergen University College, Norway B. Skaali, E. Olsen, J. Wikne –Department of Physics, University of Oslo A. Prokofiev –The Svedberg Laboratory, Uppsala University T. Krawutschke –Institute of Communication Engineering, University of Applied Sciences Cologne, Germany R. Keidel, Ch. Kofler –Center for Technology Transfer and Telecommunications, University of Applied Science Worms, Germany U. Frankenfeld –GSI, Gesellschaft für Schwerionenforschung, Darmstadt, Germany T. Alt, G. Tröger, D. Gottschalk, V. Lindenstruth, H. Tilsner –Kirchhoff Institute of Physics, University of Heidelberg, Germany B. Mota, R. Campagnolo, C. Gonzalez Gutierrez, A. Junique, L. Musa –CERN, European Organization for Nuclear Research, Geneva, Switzerland

TPC-Subsystem as used in radiation beam test in Uppsala April RCU system used in TPC sub-detector and in PHOS sub-detector (different Front-end Cards!) - Close to interaction point - Exposed to radiation TPC Front-end Electronics