Computer Organization CS224 Fall 2012 Lesson 26

Summary of Control Signals addsuborilwswbeqj RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUctr x Add x Sub Or Add x 1 x x 0 x x Sub x x x x xxx func op coding from green card Not Important

Multilevel Decoding  12-input control will be very large (2 12 = 4096)  To keep decoder size smaller, decode some control lines in each stage  Since only R-type instructions (with op = ) need function field bits, give these to ALU control func Main Control op 6 ALU Control (Local) N 6 ALUop ALUctr 2 ALU Control signals to datapath

Multilevel Decoding: Main Control Table (compare with Fig 4.22)

ALU Control  ALU used for l Load/Store: F = add l Branch: F = subtract l R-type: F depends on funct field §4.4 A Simple Implementation Scheme ALU controlFunction 0000AND 0001OR 0010add 0110subtract 0111set-on-less-than 1100NOR

ALU Control  Assume 2-bit ALUOp derived from opcode l Combinational logic derives ALU control opcodeALUOpOperationfunctALU functionALU control lw00load wordXXXXXXadd0010 sw00store wordXXXXXXadd0010 beq01branch equalXXXXXXsubtract0110 ori11OR immediateXXXXXXor0001 R-type10add100000add0010 subtract100010subtract0110 AND100100AND0000 OR100101OR0001 set-on-less-than101010set-on-less-than0111

The Main Control Unit  Control signals derived from instruction 0rsrtrdshamtfunct 31:265:025:2120:1615:1110:6 35 or 43rsrtaddress 31:2625:2120:1615:0 4rsrtaddress 31:2625:2120:1615:0 R-type Load/ Store Branch opcodealways read read, except for load write for R-type and load sign-extend and add

Datapath With Control

R-Type Instruction

Load Instruction

Branch-on-Equal Instruction

Implementing Jumps  Jump uses word address  Update PC with concatenation of l Top 4 bits of old PC l 26-bit jump address l 00  Need an extra control signal decoded from opcode 2address 31:2625:0 Jump

Datapath With Jumps Added Figure 4.24

555 Putting It All Together 32 ALUctr Clk busW RegWr 32 busA 32 busB RwRaRb bit Registers Rs Rt RegDst Extender imm16 ALUSrc ExtOp MemtoReg Clk Data In WrEn 32 Adr Data Memory 32 MemWr Instruction Fetch Unit Clk Zero Instruction[31:0] Jump Branch [21:25][16:20][11:15] [0:15] Imm16RdRsRt MUX ALU Rt Rd Mux Main Control op 6 ALU Control func 6 3 ALUop ALUctr 3 RegDst ALUSrc : Instr[5:0] Instr[31:26]

Single Cycle Processor  Advantages l Single cycle per instruction makes logic and clock simple l All machines would have a CPI of 1  Disadvantages l Inefficient utilization of memory and functional units since different instructions take different lengths of time -Each functional unit is used only once per clock cycle -e.g. ALU only computes values a small amount of the time l Cycle time is the worst case path  long cycle times! -Load instruction –PC CLK-to-Q + –instruction memory access time + –register file access time + –ALU delay + –data memory access time + –register file setup time + –clock skew l All machines would have a CPI of 1, with cycle time set by the longest instruction!

Performance Issues  Longest delay determines clock period l Critical path: load instruction l Instruction memory  register file  ALU  data memory  register file  Not feasible to vary period for different instructions  Violates design principle l Making the common case fast  We will improve performance by pipelining

 Single cycle datapath => CPI=1, CCT => long  5 steps to design a processor 1. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic  Control is the hard part  MIPS makes control easier Instructions same size Source registers always in same place Immediates same size, location Operations always on registers/immediates Summary Control Datapath Memory Processor Input Output