NTD/xNTD Signal Processing Presented by: John Bunton Signal Processing team: Joseph Pathikulangara, Jayasri Joseph, Ludi de Souza and John Bunton Plus collaboration MIT, SKA South Africa 23 November 2005

Tasks  Full NTD/xNTD beamformer (same for both)  About 1 Tbit/s input  Will take time, but want something useable now  Prototype beamformer  Reduced bandwidth and number of inputs  NTD correlator  Only one baseline  Do it in the beamformer  And eventually xNTD correlator  Not needed for some time  Initial design done  Probably parallel development with SKAMP, LFD, ???

Prototype beamformer  Reduced specification  24 MHz bandwidth, 24 inputs (expandable to 48)  Single channel FX correlator  Hardware based on MIMO test bed  4-input ADC board available but not populated  Needed six place mother board  Board to board data 28 pairs each 560Mbits/s 2 pairs for our beamformer  Motherboard up to 112 pairs plus USB  Hardware Complete  SFDR >70dB

Firmware for Prototype Beamformer  All units identical  Real to complex conversion  Ring beamformer  12bit coefficients  Selectable input to 1k filterbank  Muxes in ring to allow selection of single input to filterbank or sum of 2 to 24 inputs.  Input to correlator from previous unit.  Upgradeable to 4 or more beams and at least 3 correlations

Software for Prototype Beamformer  USB interface to PC  Selectable integration time down to 40ms  PC GUI collects data and displays it dynamically  Firmware and Software for operation as RFI measurement system complete

NTD/xNTD Beamformer  96 dual pol. inputs each 660MS/s and 8bits  1 Terabit/s  Output 33 dual pol. beams. 163Gbits/s

Cross connects  Too much data to do beamformer on single board (1Terabit/s data)  Too much data to do beamformer in single card cage  How do we interconnect?  Two technologies – one connector RJ45  LVDS– 4 pairs each 800MS/s=3.2Gbit/cable Limited by clock jitter  Rocket I/0 over 2.5Gbits/s per pair = 10Gbit/cable (10GBASE-CX4)  With Rocket I/O fit six 23 MHz bands per pair – 120 cables (4 pairs per cable)  Development board to be built to test data transport will include LVDS and Rocket I/O over RJ45 and optical  Plus short interconnects on backplane

KISS your troubles goodbye  With the interconnect problem solved (a necessity) we are free to partition the hardware in any way we want  Plan to follow the KISS principle: Keep It Simple – Stupid  Each module with have a defined function  Module design will have a linear data flow (if possible)  The designs will attempt to minimise interconnect (correlation cell)  Boards must be easy to route – easy to adopt next gen. FPGA  Adaptability of the design depends on programmability of FPGA  Eg Second Filterbank could select 4MHz to give 1kHz resolution  Ability to reroute data (in FPGA)  Eg Same data to two beamformers to get 66 beams half bandwidth  Ability to reroute RJ45 cables  Add extra modules  For more flexibility add a commercial router (add 33% to cost)

xNTD Beamformer  Break it up into two sections  Input ADCs plus oversampling polyphase filterbank  Prototype being tested  6U board with 8 channels – full system needs 24 boards  23MHz beamformer and 20.6MHz second stage filterbank (TBD)

First stage Filterbank  Divide and conquer  32 point first stage filterbanks generate ~23MHz bands (also does real to complex conversion)  Will discard outer two bands gives 15 useable bands  Oversampling filterbank to allow access to all frequencies  Oversampling by 8/7 (320MS/s 8 point version working)  Will discard redundant channels at output of second filterbank

Beamformer and Second Filterbank  All antenna data on single beamformer board  15 boards each with 192 inputs, 23MHz bands  All beams on single board, Single FPGA to do beamforming if each beam is sum of 20 single polarisation signals.  Only 20 weights per beam 660 weights for each board  Could need dual polarisation to get purity, or more inputs to increase A/Tsys up to 4 FPGAs  Single FPGA to do final filterbank but it is memory intensive  Need DRAM to buffer data into filterbanks  Will include time multiplexed correlators for calibration  Design to be finalised when specification known

xNTD Correlator  2 beams per fibre – process eight antennas on a single Router/Buffer board  Single beam correlator two pairs of FPGAs (Virtex SX35) for correlation  One input FPGA per pair (Virtex FX) and one Long Term Acc.  Five boards total for two beams Correlator for single beam

Router and Buffer  I/O to correlator chip a bottleneck  Have ~60,000 frequency channels  Correlator board processes one channel at a time  Output data rate very high  Buffer data on input board and process 256 time samples per frequency channel at a time

LFD Correlator

Correlation Cell  Standard systolic array design over 208 LVDS inputs  Solution – Correlation Cell  Provide storage for two sets of data 16 values each  Sixteen times reduction in I/O per multiplier  xNTD uses groups of 4 cells  Input reduced to 96 LVDS for xNTD

Possible pulsar de-disperser  Break into 8 MHz bands  Continuous convolution of bands (120ns time resolution)  Dispersion up to 480 us  Multiple DMs per V4SX35 de-disperser  Folding as well

Questions ?

Contacts John Bunton Senior Principle Research Scientist ICT Centre Tel: For more information, see or contact: