CSET 4650 Field Programmable Logic Devices Dan Solarek Introduction to VHDL An Overview / Review

2 What is VHDL? VHDL = VHSIC Hardware Description Language where VHSIC = Very High Speed Integrated Circuit A technology independent, standard language for: hardware description simulationsynthesis

3 What is VHDL? VHDL is a programming language that has been designed and optimized for describing the behavior of digital systems. Syntax is similar to C (actually, more like Ada) It is highly typed – includes a rich set of data types Allows concurrent processing Not a general purpose programming language

4 History of VHDL Development Outgrowth of the DARPA VHSIC Program Vendors designing large chips needed to exchange data describing their designs IBM, Texas Instruments, and Intermetrics got the contract in 1983 and released VHDL 7.2 in 1985 Released to the IEEE for standardization in 1986 Became IEEE Std Reballoted/upgraded to IEEE Std Released IEEE Std , STD_LOGIC_ valued logic definition, math functions for std_logic

5 Why VHDL? It is a Standard Data Exchange medium between Vendors Communications medium between CAD Tools Not Proprietary Promotes interoperability and design re-use Not technology-specific Human-Readable Can be used to describe the behavior of a design, or to synthesize the design itself Supports a wide range of abstraction levels Can model a system, board, chip, register-transfer-level (RTL), or gate level designs

6 VHDL Features Supports Hierarchy Flexible design methodology: Top-down, bottom-up, or both Has elements to make large-scale design easier e.g., components, functions, procedures, packages, configuration Supports three types of Supports three types of modeling styles: Behavioral (sequential statement model [like a program]) Dataflow (concurrent statement modeling) Structural (for connecting components) Test Benches can be written in the same language circuits can be verified by simulation before synthesis Propagation delays, min-max delays, setup and hold timing, timing constraints, etc. can all be described naturally or mixed

7 Basic Hardware Design Flow

8 VHDL Design Flow 1. Hierarchical / block diagram Figuring out the basic approach and building blocks at the block-diagram level. Large logic designs are usually hierarchical, and VHDL gives you a good framework for defining modules and their interfaces and filling in the details later. 2. Coding Actual writing of VHDL code for modules, their interfaces, and their internal details.

9 Design Flow 3. Compilation Analyses your code for syntax errors and checks it for compatibility with other modules on which it relies. Compilation also creates the internal information that is needed for simulation. 4. Simulation A VHDL simulator allows you to define and apply inputs to your design, and to observe its outputs. Simulation is part of a larger step called verification. A functional verification is performed to verify that the circuit’s logical operation works as desired independent of timing considerations and gate delays.

10 Design Flow 5. Synthesis Converting the VHDL description into a set of primitives or components that can be assembled in the target technology. For example, with PLDs or CPLDs, the synthesis tool may generate two-level sum-of products equations. With ASICs, it may generate a netlist that specifies how the gates should be interconnected. 6. Fitting / Placement & Routing Maps the synthesized components onto physical devices.

11 Design Flow 7. Timing verification At this stage, the actual circuit delays due to wire lengths, electrical loading, and other factors are known, so precise timing simulation can be performed. Study the circuit’s operation including estimated delays, and verify that the setup, hold, and other timing requirements for sequential devices (like flip-flops) are met.

12 Elements of VHDL Syntax (the rules) Five design units (or elements) Identifiers (naming constraints) Data objects (what you name) Data types (enumerated, integer, arrays, etc.) Examples

13 VHDL Provides Five Design Units Entity Declaration Specifies the NAME and lists the interface PORTS Architecture Body Models the actual circuit “guts” within an entity Configuration Declaration Identifies which arch. should be used with an entity Specifies location of components used within arch. Package Declaration – like a header file in C Package Body – like an implementation file in C Packages are libraries containing type definitions, overloaded operators, components, functions, and procedures. They have a “declarative” section and a BODY section. Elements of a Package can be used by many entities in a design, or many designs. Our initial examples will focus on the first three design units.

14 VHDL Identifiers (Names) Basic identifier starts with a letter made up of letters, numbers, and underscore “_” character cannot end with an underscore case-insensitive: MY_Signal_Name = my_signal_name Extended Identifier any text within 2 backslashes e.g., \2FOR$\ \-23signal\ etc. case is significant: \COUNT\ not equal to \count\, and \FRAMUS\ not equal to basic identifier FRAMUS Not often used – not necessarily supported in synthesis !! not recommended

15 Four Classes of Data Objects Constant Holds a single value of a given type – cannot change. Variable Holds a single value of a given type. New value of same type can be “assigned” – (instantly) Signal Holds a LIST of values of a given type. Present value + a set of possible future values New values can be assigned at some future time – not now! Signals have ATTRIBUTES: [signal’attribute] File Contains a sequence of values of one or more types. Usually read or written to using procedures For simulation – not synthesis analogous to a “wire”

16 Data Types Scalar Types Enumerated : a list of values Integer Floating Point Physical : with units, for physical quantities Composite Types Array (all of same type) Record (can be different types) Access Type File Type

17 Enumerated Types CHARACTER – one of the ASCII set BOOLEAN – can be FALSE or TRUE BIT – can be ‘0’ or ‘1’ (note single quotes) STD_LOGIC Has NINE legal values: ‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’ Example Declarations Type CAR_STATE is (back, stop, slow, medium, fast); Subtype GO_KART is CAR_STATE range stop to medium; Type DIGIT is (‘0’, ‘1’, ‘2’, ‘3’, ‘4’, ‘5’, ‘6’, ‘7’, ‘8’, ‘9’ ); IEEE std_logic_1164 package

18 Integers All implementations support 32-bit integers, with a range of values from –(2 31 – 1) to +(2 31 – 1) Integer data types with a smaller rage can be defined to save hardware (no sense forcing a 32-bit counter when you need a 4-bit counter) Examples of legal integers E2 0 98_71_28 (Underscores can be thrown in anywhere, and don’t change the value of the number.)

19 Integers Type Declarations Type INDEX is range 0 to 15; Type WORD_LENGTH is range 31 downto 0; Subtype DATA_WORD is WORD_LENTH range 15 downto 0; Object Declarations Constant MUX_ADDRESS: INDEX := 5; Signal DATA_BUS: DATA_WORD;

20 Arrays An Array of type BIT is called a BIT_VECTOR signal MYSIG : IN BIT_VECTOR( 0 to 3); An Array of type STD_LOGIC is called a STD_LOGIC_VECTOR signal yourSIG : OUT BIT_VECTOR( 31 downto 0); A STRING is a character array csonstant GREETING: STRING := “Hello!”;

21 VHDL Key Idea A key idea in VHDL is to define the interface of a hardware module while hiding its internal details. A VHDL entity is simply a declaration of a module’s inputs and outputs, i.e., its external interface signals or ports. A VHDL architecture is a detailed description of the module’s internal structure or behavior. entity architecture interface

22 VHDL Interface - Ports You can think of the entity as a “wrapper” for the architecture hiding the details of what’s inside providing “ports” to other modules input port entity architecture output port

23 VHDL Conceptual Model VHDL actually allows you to define multiple architectures for a single entity it also provides a configuration management facility that allows you to specify which architecture to use during a particular synthesis run entity architecture 1 architecture 2 configuration

24 VHDL Program File In the text file of a VHDL program: the entity, architecture, and configuration declarations are all separated not nested as the previous diagram may have implied We will use white space to set them apart mydesign.vhd entity architecture configuration

25 Entity Declaration Specifies the name of the entity Lists the set of interface PORTS PORTS are SIGNALS that enter or leave the entity This is the “black box,” or block diagram view Half-Adder A B SUM CARRY

26 Entity Declaration entity half_adder is port( A, B : in BIT; SUM, CARRY : out BIT); end half_adder; entity half_adder is port( A, B : in BIT; SUM : out BIT; CARRY : out BIT ); end entity half_adder; no “;” after last signal end of port statement NAME MODE TYPE optional words, but recommended White space is ignored

27 Entity Declaration entity half_adder is port( A, B : in BIT; SUM, CARRY : out std_logic); end half_adder; entity half_adder is port( A, B : in std_logic; SUM : out std_logic; CARRY : out std_logic ); end entity half_adder; Using IEEE 1164 standard signals and data types: TYPE

28 VHDL Signal Modes in means input-ONLY, you cannot use a mode in signal on the LEFT side of an equation (that is, you can’t assign a new value to inputs) in – means input-ONLY, you cannot use a mode in signal on the LEFT side of an equation (that is, you can’t assign a new value to inputs) out means output-ONLY, you cannot use a mode out signal on the RIGHT side of an equation (that is, you can’t “use” the outputs) out – means output-ONLY, you cannot use a mode out signal on the RIGHT side of an equation (that is, you can’t “use” the outputs) inout means bi-directional, like a three-state bus, for example. inout – means bi-directional, like a three-state bus, for example. This mode is typically used for three-state input/output pins on PLDs buffer – means the signal is an output of the entity, and its value can also be read inside the entity’s architecture

29 Example: LogicFcn entity architecture A B C Y ports

30 Entity Declaration for LogicFcn library IEEE; use IEEE.std_logic_1164.all; entity LogicFcn is port ( A: in std_logic; B: in std_logic; C: in std_logic; Y: out std_logic ); end entity LogicFcn; A B C Y

31 Architecture Body Specifies the internal circuitry of an entity, using any one of the following modeling styles: 1.As a set of interconnected components, as wired (called structural modeling) 2.As a set of concurrent signal assignment statements (called dataflow modeling) 3.As a set of sequential assignment statements, i.e., a “process” (called behavioral modeling) 4.As any combination of the above (called mixed modeling)

32 Parts of Architecture Body architecture ARCH_NAME of ENTITY_NAME is begin end ARCH_NAME;

33 Architecture Body (Dataflow) architecture dataflow of LogicFcn is begin Y <= (not A and not B) or C; end dataflow; With a signal assignment statement:

34 Architecture Body (Dataflow) architecture dataflow of LogicFcn is begin Y <= '1' when (A = '0' AND B = '0') OR (C = '1') else '0'; end dataflow; With a conditional signal assignment statement:

35 Architecture Body (Behavioral) architecture behavioral of LogicFcn is begin fcn: process (A,B,C) begin wait on A,B,C; if (A = '0' and B = '0') then Y <= '1'; elsif C = '1' then Y <= '1'; else Y <= '0'; end if; end process; end behavioral; “Label:” Name of process Sensitivity List - The Process will be executed anytime there is an EVENT (change of state) on one of these signals. WAIT ON statement - has same effect as sensitivity list. CANNOT USE BOTH. Processes with WAIT statements cannot have sensitivity lists !! Statements within Processes are executed sequentially. (This is a single IF statement) The process, however, executes concurrently with other processes and concurrent statements in the architecture. process Values are assigned to signals when process suspends

36 Architecture Body (Structural) A B C Y entity architecture Internal signals are LOCAL to the Architecture, and cannot be seen outside it ! notA notB andSignal signals

37 Architecture Body (Structural) architecture structural of LogicFcn is signal notA, notB, andSignal: std_logic; begin i1: inverter port map (i => A, o => notA); i2: inverter port map (i => B, o => notB); a1: and2 port map (i1 => notA, i2 => notB, y => andSignal); o1: or2 port map (i1 => andSignal, i2 => C, y => Y); end structural; LOCAL SIGNALS are declared within the architecture and they have no MODE (IN, OUT, etc.) COMPONENT declarations may go here These are COMPONENT INSTANTIATIONS

38 Components for Structural Model library IEEE; use IEEE.std_logic_1164.all; package primitive is component AND2 port ( i1: in std_logic; i2: in std_logic; y: out std_logic ); end component; component OR2 port ( i1: in std_logic; i2: in std_logic; y: out std_logic ); end component; component INVERTER port ( i: in std_logic; o: out std_logic ); end component; end primitive; these are component declarations