1 COMP541 More on State Machines; and Video Scanout Montek Singh Feb 16, 2010

Outline  Last Friday’s lab Tips/discussion Tips/discussion  Look at Verilog coding practices Avoid generating latches Avoid generating latches Parameterized Modules Parameterized Modules  How to generate video signal 2

3 What did you have trouble with in lab?

Testing  How do you simulate/test a module that outputs a signal every millionth time? 4

Off By One?  Did you have problems if you designed a counter out of one-digit modules? 5

Good Verilog Practices  Best to use single clock for all FFs Make all signals synchronous to one clk Make all signals synchronous to one clk  no posedge button or posedge pulse  –not supported by current board Avoids “weird” and frustrating problems Avoids “weird” and frustrating problems  Multiple modules Tested individually Tested individually Top level has input and outputs Top level has input and outputs  One module per file Just to make it easier to follow and test Just to make it easier to follow and test 6

Button Debounce  Mechanical switches can “bounce”  May get a fast series of Hs and Ls 10s of milliseconds 10s of milliseconds  How do we avoid problems? 7

Button Debounce and Synchronize  Let’s try to make it simpler this time! Use it as input to test in an always statement that’s clocked by the master clock Use it as input to test in an always statement that’s clocked by the master clock State machine to detect down/up? State machine to detect down/up?  Wait for N clock cycles and then use it! 8

What else did you have trouble with in lab? 9

10 Assignment (of signals)  Continuous  Procedural Note there are two uses for always Note there are two uses for always  To generate FFs and latches (plus gates)  To generate combinational logic only –Latter does not introduce unnecessary FFs … –… if synthesizer detects all possibilities covered (i.e. no state needed)  Look at the synthesizer log

Procedural Assignment 1 module C2(output reg C = 0, input A, input B); (A or B) case ({A, B}) 2'b11: C <= 1; default: C <= 0; endcaseendmodule  Schematic next page 11

12Schematic  LUT is a look-up table  Double clicking it shows

Procedural Assignment 2 module C1(output reg C = 0, input A, input B); (A or B) begin if(A == 1 && B == 1) C <= 1; endendmodule  Synthesizer now says WARNING:Xst:737 - Found 1-bit latch for signal. WARNING:Xst: The value init of the FF/Latch C hinder the constant cleaning in the block C1. 13

14Schematic  LDE is latch  Small box is clock driver

15 In fact…  If I change the INIT of C like it says output reg C = 1 output reg C = 1  Synthesizer says INFO:Xst: Contents of register in unit never changes during circuit operation. The register is replaced by logic. INFO:Xst: Contents of register in unit never changes during circuit operation. The register is replaced by logic.

Schematic module C1(output reg C = 1, input A, input B); (A or B) begin if(A == 1 && B == 1) C <= 1; endendmodule 16

Parameterized Modules 2:1 mux: module mux2 #(parameter width = 8) // name and default value #(parameter width = 8) // name and default value (input [width-1:0] d0, d1, (input [width-1:0] d0, d1, input s, input s, output [width-1:0] y); output [width-1:0] y); assign y = s ? d1 : d0; assign y = s ? d1 : d0;endmodule Instance with 8-bit bus width (uses default): mux2 mux1(d0, d1, s, out); mux2 mux1(d0, d1, s, out); Instance with 12-bit bus width: mux2 #(12) lowmux(d0, d1, s, out);

VGA Monitors 18

19 How Do Monitors Work?  Origin is TV, so let’s look at that LCDs work on different principle, but all signaling still derived from TV of 1940s LCDs work on different principle, but all signaling still derived from TV of 1940s  Relies on your brain to do two things Integrate over space Integrate over space Integrate over time Integrate over time

Many Still Images  Video (and movies) are a series of stills If stills go fast enough your brain interprets as moving imagery If stills go fast enough your brain interprets as moving imagery  Hz or more to not see flicker In fact, even single “still” image displayed repeatedly over time In fact, even single “still” image displayed repeatedly over time Phosphor persistence varies Phosphor persistence varies 20

Cathode Ray Tube 21 From wikipedia:

Deflection Coils 22

Simple Scanning TV  Electron beam scans across  Turned off when Scanning back to the left (horizontal retrace) Scanning back to the left (horizontal retrace) Scanning to the top (vertical retrace) Scanning to the top (vertical retrace) 23

Scanning  TVs use interlacing Every other scan line is swept per field Every other scan line is swept per field Two fields per frame (30Hz) Two fields per frame (30Hz) Way to make movement less disturbing Way to make movement less disturbing  Computers use progressive scan Whole frame refreshed at once Whole frame refreshed at once 60Hz or more, 72Hz looks better 60Hz or more, 72Hz looks better 24

Color  Three colors of phosphor  Beams hit each  Black – beam off  White – all on 25 Picture is a bit misleading. Mask (or aperture grill) ensures beams hit only correct color phosphor.

Aside  Frustrated with Verilog  See what to do to relieve stress  Educational too 26

What about LCD?  We’ll talk about how they work later  They don’t scan  However, signaling is the same! For compatibility For compatibility  Same goes for micro-mirror projectors 27

28 VGA Signaling  RGB and two synchronization pulses, horizontal and vertical

VGA Timing  You supply two pulses, hsync and vsync, that let the monitor lock onto timing  One hsync per scan line  One vsync per frame  Continuous Don’t stop hsync Don’t stop hsync 29 Image from dell.com

Horizontal Timing Terms  hsync pulse  Back porch (left side of display)  Active Video Video should be blanked (not sent) at other times Video should be blanked (not sent) at other times  Front porch (right side) 30 Picture not accurate for our case; just for illustration. Video and HSYNC not on same wire

Horizontal Timing Horizontal Dots Horiz. Sync Polarity NEG Scanline time (A) us Sync pulse length (B) 3.77 us Back porch (C) 1.89 us Active video (D) us Front porch (E) 0.94 us Image from This diagram shows video as a digital signal. It’s not – video is an analog level.

Vertical Timing (note ms, not us) 32 Vert. Sync Polarity NEG Vertical Frequency 60Hz Total frame time (O) ms Sync length (P) 0.06 ms Back porch (Q) 1.02 ms Active video (R) ms Front porch (S) 0.35 ms

Timing as Pixels  Easiest to derive all timing from single-pixel timing  How “long” is a pixel? Active video / number of pixels Active video / number of pixels us / 640 = 39.32ns us / 640 = 39.32ns Conveniently close to 25 MHz – just use that Conveniently close to 25 MHz – just use that Actual VESA spec is MHz Actual VESA spec is MHz 33

Standards  640 x 480 (sometimes x 60Hz) is “VGA” I will give you spec sheets in lab I will give you spec sheets in lab  You can try for 800x600 at 60 Hz (40 MHz exactly) or 800x600 at 72 Hz (50 MHz exactly) or 800x600 at 72 Hz (50 MHz exactly)  Note that some standards have vsync and hsync positive true, some negative true – choose correct one 34

Color Depth  Voltage of each of RGB determines color  3-bit, 2-bit color here  All on for white 35

What To Do Friday 1. First finish previous lab 2. Make Verilog module to generate hsync, vsync, horizontal count, vertical count, and signal to indicate active video hsync, vsync, horizontal count, vertical count, and signal to indicate active video 3. Use higher-level module to drive RGB using counts gated by active Just do something simple; need to meet 25MHz constraint Just do something simple; need to meet 25MHz constraint 4. Later will use memory addressed by counts to make terminal 36

37 What do you Need for VGA?  Think first Need counter(s)? Need counter(s)? Will you need a state machine? Will you need a state machine?  Sketch out a design Block diagram Block diagram  Test individually in lab  Keep in Mind Verilog has all these operators (and more; see Verilog ref.) Verilog has all these operators (and more; see Verilog ref.) ==,, = ==,, =

Next week’s lab: Character Terminal?  No frame buffer  Character terminal 38

Future Labs Preview  VGA timing generator  Character terminal (learn memories)  MIPS datapath  Add load/store  Add branching  Peripherals  Final project 39

VGA Links  VGA Timing  Code (more complex than you want)  Interesting Liquid Crystals by S. Chandrasekhar, Cambridge Univ. Press Liquid Crystals by S. Chandrasekhar, Cambridge Univ. Press 40

Next Time  Sequential Timing  Metastability  Homework due 41