1 PIXEL H. Wieman HFT CDO LBNL Feb-2008

2 topics  Pixel specifications and parameters  Pixel silicon  Pixel Readout uSTAR telescope tests  Mechanical organization

3 Pixel geometry 2.5 cm radius 8 cm radius Inner layer Outer layer End view One of two half cylinders 20 cm  coverage +-1 total 40 ladders

4 Some pixel features and specifications Pointing resolution(13  19GeV/p  c)  m LayersLayer 1 at 2.5 cm radius Layer 2 at 8 cm radius Pixel size30  m X 30  m Hit resolution10  m rms Position stability6  m (20  m envelope) Radiation thickness per layer X/X0 = 0.28% Number of pixels164 M Integration time (affects pileup) 0.2 ms Radiation tolerance300 kRad Rapid installation and replacement to cover rad damage and other detector failure Installation and reproducible positioning in a shift

5 Silicon program pixel chips (MAPS) produced by IReS/LEPSI  IPHC (Strasbourg) M. Winter C. Hu C. Colledani W. Dulinski A. Himmi A. Shabetai M. Szelezniak I. Valin

6 MAPS Properties: Signal created in low-doped epitaxial layer (typically ~10-15 μm) Sensor and signal processing integrated in the same silicon wafer Standard commercial CMOS technology

7 IPHC Functional Sensor Development Data Processing in RDO and on chip by generation of sensor. The RDO system design evolves with the sensor generation. 30 x 30 µm pixels CMOS technology Full Reticule = 640 x 640 pixel array Mimostar 2 => full functionality 1/25 reticule, 1.7 µs integration time (1 MHz clk), analog output. (in hand and tested) All sensor families: Phase-1 and Ultimate sensors => digital output (in development) Leo Greiner next year Phase 1 – Nov 2008 Ultimate – Nov 2009

8 Grzegorz Deptuch MIMOSTAR 2/3 technology

9 Phase 1 / Ultimate technology (MIMOSA8/16/22)

10 IHCP Marc Winter et al Preliminary tests in Saclay of chips with 20 µm and 14 µm thick epitaxy layer Fe55 tests Noise and Fixed pattern noise measured In beam MIP detection efficiency measured with silicon strip telescope

11 IHCP Marc Winter et al

12 IHCP Marc Winter et al

13 Silicon summary, development of STAR pixels  Finished MIMOSTAR 2 with readout development  Working on MIMOSTAR 3 studies  Fab Phase 1 based on MIMOSA16/22 technology (digital output, no zero suppression)  Fab Ulitimate based on MIMOSA16/22 and SUZE technology (digital with zero suppression)  Issues  MIMOSTAR 3 yield  Radiation hardness (bulk damage) uReduce temperature uInvestigate silicon improvements

14 Readout system LBNL Leo Greiner Xiangming Sun Michal Szelezniak Thorsten Stezelberger Chinh Vu Howard Matis

15 1 m – Low mass twisted pair 6 m - twisted pair System Design – Physical Layout Sensors, Ladders, Carriers (interaction point) LU Protected Regulators, Mass cable termination RDO Boards DAQ PCs Magnet Pole Face (Low Rad Area ?) DAQ Room Power Supplies Platform 30 m 100 m - Fiber optic cables Leo Greiner

16 Detailed System Structure – System Level Functioning

17 Data Rates - Parameters  2.5 hits / cluster.  1 kHz average event rate.  10 inner ladders, 30 outer ladders.  No run length encoding X X R = 2.5 R = us 640 us Integration Time Radius Leo Greiner L

18 Data Rates  Ultimate => 49.7 MB / s raw addresses.  Phase–1 => 59.6 MB / s raw addresses  Dead time primarily limited by number of externally allocated readout buffers

19 Prototype test in STAR with 3 Sensor Telescope Our goal was to test functionality of a prototype MIMOSTAR2 detector in the environment at STAR in the run at STAR. We obtained information on:  Charged particle environment near the interaction region in STAR.  Performance of our cluster finding algorithm.  Performance of the MIMOSTAR2 sensors.  Functionality of our tested interfaces to the other STAR subsystems.  Performance of our hardware / firmware as a system.  The noise environment in the area in which we expect to put the final PIXEL detector. Stack of 3 MIMOSTAR2 pixel chips, Chip dimension: 4 mm X 4mm, 128 X 128 pixels

20 Telescope DAQ

21 Distribution of track angles in Mimostar2 telescope Xiangming Sun Michal Szelezniak

22 Summary of 2007 Au + Au test in STAR  Integrated background small compared to real interaction signals  No noise pickup  Hit rate as expected  Readout system worked well in the STAR trigger DAQ environment  Cluster finding system worked well

23 Digital data transfer test (LVDS)  200 MHz test  160 MHz required  40 data pairs (one ladder worth)  Programmed tuning of each IO delay on Virtex5 FPGA, 7.5 ps steps  No bit errors, 12 hr, random data ladder data generator 42 fine gauge twisted pairs 6 m robust twisted pair cable eye pattern Virtex5 development board mother board DDL/SIU fiber link 5 ns Duplicate ~10 times for final system

24 Mechanical Program  Eric Anderssen, LBNL engineer working on ATLAS pixels is phasing into our pixel program – full time in April 2008 (carbon composite expert)  Contracted ARES company for analysis on cooling, precision mount design and refinement of ladder stability. uPhone meetings weekly uReport due end February

25 HFT Mechanical requirements Full self consistent spatial mapping prior to installation Installation and removal does not disturb mapping Rapid replacement 20 Micron stability (mapping of BaBar with visual coordinate machine)

26 Rapid installation (8hr) while preserving spatial map

27 Summary  Silicon design and development carried out by IPHC uadditional testing at LBNL  Readout system with STAR integration, well advanced, LBNL  Mechanical work uProject engineer: Eric Anderssen LBNL uConsulting work: ARES corporation, Los Alamos branch

28 Next slide backup

29 MIMOSTAR 3 edge good MIMOSTAR 3 center bad

30 Silicon Cost Chips per ladder10 Ladders per Detector40 Number of Detector Copies 4 Number of working chips1600 Yield60% Total chips2700 Total wafers44 Wafer Cost Each7.2 k$ Wafer Costs316 k$ Mask Cost220 k$ Total536 k$ 8 inch wafers 60 chips/wafer 237 k$ incremental silicon cost for the 3 spare copies

31 yearly dose numbers  Au + Au  RHIC II luminosity: 7X /(cm 2 sec)  Weeks per year operation: 25  Fraction of up time: 60%  radius: 2.5 cm upion dose: 73 kRad uUPC electron dose: 82 kRad uTotal dose: 155 kRad uTLD measured projection: 300 kRad  radius: 8 cm upion dose: 7 kRad uUPC electron dose: 2 kRad uTotal dose: 9 kRad uTLD measured projection: 29 kRad

32 RDO Board(s) New motherboard Two board System – Virtex-5 Development board mated to a new HFT motherboard Xilinx Virtex-5 Development Board Digital I/O LVDS Drivers 4 X >80 MHz ADCs PMC connectors for SIU Cypress USB chipset SODIMM Memory slot Serial interface Trigger / Control input FF1760 Package 800 – 1200 I/O pins 4.6 – 10.4 Mb block RAM 550 MHz internal clock Note – This board is designed for development and testing. Not all features will be loaded for production. Leo Greiner