FE8113 ”High Speed Data Converters”

Part 3: High-Speed ADCs

G.Geelen et.al: “A 90nm CMOS 1.2V 10b Power and Speed Programmable Pipelined ADC With 0.5pJ/Conversion-Step”, IEEE ISSCC2006A 90nm CMOS 1.2V 10b Power and Speed Programmable Pipelined ADC With 0.5pJ/Conversion-Step” S-T.Ryu et.al: “A 10b 50MS/s Pipelined ADC With Opamp Current Reuse”, IEEE ISSCC2006A 10b 50MS/s Pipelined ADC With Opamp Current Reuse” T.Sepke et.al: “Comparator-Based Switched Capacitor Circuits For Scaled CMOS TEchnologies”, IEEE ISSCC2006Comparator-Based Switched Capacitor Circuits For Scaled CMOS TEchnologies” S.Gupta et.al: “A 1GS/s 11b Time-Interleaved ADC in 0.13µm CMOS”, IEEE ISSCC2006A 1GS/s 11b Time-Interleaved ADC in 0.13µm CMOS” Papers 10, 11, 12 and 13

G.Geelen et.al: “A 90nm CMOS 1.2V 10b Power and Speed Programmable Pipelined ADC With 0.5pJ/Conversion-Step”A 90nm CMOS 1.2V 10b Power and Speed Programmable Pipelined ADC With 0.5pJ/Conversion-Step” 10b Pipelined ADC  This converter: 0.5pJ

G.Geelen et.al: “A 90nm CMOS 1.2V 10b Power and Speed Programmable Pipelined ADC With 0.5pJ/Conversion-Step”A 90nm CMOS 1.2V 10b Power and Speed Programmable Pipelined ADC With 0.5pJ/Conversion-Step” Sampling to ground  Sampling to virtual ground minimizes 1/f-noise and opamp offset effects. However, high-frequency opamp noise is added during sampling Large input transistor to minimze 1/f-noise

G.Geelen et.al: “A 90nm CMOS 1.2V 10b Power and Speed Programmable Pipelined ADC With 0.5pJ/Conversion-Step”A 90nm CMOS 1.2V 10b Power and Speed Programmable Pipelined ADC With 0.5pJ/Conversion-Step” Two-stage Miller opamp Folded cascode first stage  A 0 ~ g m /g o  A 0 > 65dB over a large bias range

G.Geelen et.al: “A 90nm CMOS 1.2V 10b Power and Speed Programmable Pipelined ADC With 0.5pJ/Conversion-Step”A 90nm CMOS 1.2V 10b Power and Speed Programmable Pipelined ADC With 0.5pJ/Conversion-Step” Measured dynamic performance

G.Geelen et.al: “A 90nm CMOS 1.2V 10b Power and Speed Programmable Pipelined ADC With 0.5pJ/Conversion-Step”A 90nm CMOS 1.2V 10b Power and Speed Programmable Pipelined ADC With 0.5pJ/Conversion-Step” Performance summary

S-T.Ryu et.al: “A 10b 50MS/s Pipelined ADC With Opamp Current Reuse”A 10b 50MS/s Pipelined ADC With Opamp Current Reuse” Pipelined ADC  Two first stages: N-Input MDAC  Two last stages: P-Input MDAC P- and N-input MDACs share bias current

S-T.Ryu et.al: “A 10b 50MS/s Pipelined ADC With Opamp Current Reuse”A 10b 50MS/s Pipelined ADC With Opamp Current Reuse” MDAC operation with simplified opamp schematic

S-T.Ryu et.al: “A 10b 50MS/s Pipelined ADC With Opamp Current Reuse”A 10b 50MS/s Pipelined ADC With Opamp Current Reuse” Opampwith both P and N inputs  Gain-boosted opamp with capacitive CMFB  NMOS boost amplifiers. Capacitive level shifting allows NMOS boost amplifiers for both P and N cascodes

S-T.Ryu et.al: “A 10b 50MS/s Pipelined ADC With Opamp Current Reuse”A 10b 50MS/s Pipelined ADC With Opamp Current Reuse” 0.18µm CMOS, 1.8V supply Power consumption: 50MS/s DNL: +/- 0.2 LSB, INL: +/- 0.4LSB ENOB: 9.2b/8.8b for 1MHz/20MHz inputs SFDR ~ 70dB

T.Sepke et.al: “Comparator-Based Switched Capacitor Circuits For Scaled CMOS TEchnologies”Comparator-Based Switched Capacitor Circuits For Scaled CMOS TEchnologies” High-gain opamps without reduced signal swing is difficult to design in modern technologies Open-loop amplification avoids this, but requires calibration New appraoch: Use a comparator to detect virtual ground  It is easier to detect the virtual ground than forcing it  Will work for all sampled-data, switch-cap systems (filters, pipeline stages ++)

T.Sepke et.al: “Comparator-Based Switched Capacitor Circuits For Scaled CMOS Technologies”Comparator-Based Switched Capacitor Circuits For Scaled CMOS Technologies” Comparator/loop delay results in overshoot  Use a coarse and a fine current source  With constant delay and current, this leads to a constant offset at the output

T.Sepke et.al: “Comparator-Based Switched Capacitor Circuits For Scaled CMOS Technologies”Comparator-Based Switched Capacitor Circuits For Scaled CMOS Technologies” 10b pipeline prototype design  1.5b stages, cascaded with no scaling Proof-of-concept design

T.Sepke et.al: “Comparator-Based Switched Capacitor Circuits For Scaled CMOS Technologies”Comparator-Based Switched Capacitor Circuits For Scaled CMOS Technologies” Continuous-time comparator

T.Sepke et.al: “Comparator-Based Switched Capacitor Circuits For Scaled CMOS Technologies”Comparator-Based Switched Capacitor Circuits For Scaled CMOS Technologies” 10b 8MHz pipeline 0.18µm CMOS, 1.8V supply Power consumption: 8MS/s DNL: 0.33/-0.28 LSB, INL: 1.59/-1.13 LSB Input-refferd rms noise: 0.65 LSB FOM: 0.3pJ/b

S.Gupta et.al: “A 1GS/s 11b Time-Interleaved ADC in 0.13µm CMOS”A 1GS/s 11b Time-Interleaved ADC in 0.13µm CMOS” 11b 1GS/s TI-converter Input S/H switch to eliminate timing errors Double sampling in sub-ADCs to reduce the number of sub-converters

S.Gupta et.al: “A 1GS/s 11b Time-Interleaved ADC in 0.13µm CMOS”A 1GS/s 11b Time-Interleaved ADC in 0.13µm CMOS” Double-sampled TI-architecture

S.Gupta et.al: “A 1GS/s 11b Time-Interleaved ADC in 0.13µm CMOS”A 1GS/s 11b Time-Interleaved ADC in 0.13µm CMOS” Timing scheme

S.Gupta et.al: “A 1GS/s 11b Time-Interleaved ADC in 0.13µm CMOS”A 1GS/s 11b Time-Interleaved ADC in 0.13µm CMOS” 11b 1GSps TI-converter 0.13µm CMOS, 1.2V/2.5V supply Peak SNR: 58.6dB, peak SNDR: 55dB SNDR is 52dB with 400MHz input frequency FOM < 0.5pJ