Overview Why VLSI? Moore’s Law. ASIC: Abstraction and Hierarchy. FPGA: cheaper and programmable ASIC Note:

VLSI and you Microprocessors: DRAM/SRAM. Special-purpose processors. personal computers; microcontrollers. DRAM/SRAM. Special-purpose processors. Many other applications: telecom, DSP,etc. Note:

Moore’s Law Gordon Moore: co-founder of Intel. Predicted that number of transistors per chip would grow exponentially (double every 18 months). Exponential improvement in technology is a natural trend: steam engines, dynamos, automobiles. Note:

Moore’s Law plot Note:

Overview Why VLSI? Moore’s Law. ASIC: Abstraction and Hierarchy. FPGA: cheaper ASIC Note:

ASIC and FPGA Application-specific integrated circuit design Field programmable gate array Note:

ASIC Top-down approaches Note:

Levels of abstraction Specification: function, cost, etc. Architecture: large blocks. Logic: gates + registers. Circuits: transistor sizes for speed, power. Layout: determines parasitics. Note:

Design abstractions specification behavior function cost logic circuit English Executable program Sequential machines Logic gates transistors rectangles specification Throughput, design time Function units, clock cycles Literals, logic depth nanoseconds microns behavior function cost register- transfer logic Note: circuit layout

CAD Tools specification behavior logic circuit layout English Synopsys VHDL/verilog (schematic) Gate netlist Transistor netlist specification Synopsys Cadence behavior register- transfer logic Note: circuit layout

ASIC: Hierarchical name Interior view of a component: components and wires that make it up. Exterior view of a component = type: body; pins. cout Full adder Note: sum a b cin

ASIC:Instantiating component types Each instance has its own name: add1 (type full adder) add2 (type full adder). Each instance is a separate copy of the type: cout Add1.a Add2.a Note: Add2(Full adder) Add1(Full adder) sum sum a a b b cin cin

Net lists and component lists net1: top.in1 in1.in net2: i1.out xxx.B topin1: top.n1 xxx.xin1 topin2: top.n2 xxx.xin2 botin1: top.n3 xxx.xin3 net3: xxx.out i2.in outnet: i2.out top.out Component list: top: in1=net1 n1=topin1 n2=topin2 n3=topine out=outnet i1: in=net1 out=net2 xxx: xin1=topin1 xin2=topin2 xin3=botin1 B=net2 out=net3 i2: in=net3 out=outnet Note:

Component hierarchy top i1 xxx i2 Note:

Hierarchical names Typical hierarchical name: top/i1.foo component pin Note:

Layout and its abstractions Layout for dynamic latch: Note:

Stick diagram Note:

Transistor schematic Note:

Mixed schematic Note: inverter

Characteristics of ASIC Expensive Many cycles of design: Simulation, synthesis Design for testing (DFT) Note:

Layout of ASIC Pentium IV Technology: 0.13 um Area: 35 mm square Speed: 2.2GHz Power: 55 W

Design abstractions specification behavior function cost logic circuit English Executable program Sequential machines Logic gates transistors rectangles specification Throughput, design time Function units, clock cycles Literals, logic depth nanoseconds microns behavior function cost register- transfer logic circuit layout

CAD Tools specification behavior logic circuit layout English Synopsys VHDL/verilog (schematic) Gate netlist Transistor netlist specification Synopsys Cadence behavior register- transfer logic circuit layout

Characteristics of FPGA Programmability Simulation, synthesis Test Note:

Layout of FPGA

Top-down vs. bottom-up design Top-down design adds functional detail. Create lower levels of abstraction from upper levels. Bottom-up design creates abstractions from low-level behavior. Good design needs both top-down and bottom-up efforts.

Design abstractions specification behavior function cost logic circuit English Executable program Sequential machines Logic gates transistors rectangles specification Throughput, design time Function units, clock cycles Literals, logic depth nanoseconds microns behavior function cost register- transfer logic circuit layout

CAD Tools specification behavior logic circuit layout English VHDL/verilog (schematic) Gate netlist Transistor netlist specification behavior Xilinx Foundation tools register- transfer logic circuit layout

Contents of the Course ASIC FPGA Transistor and Layout Gate and Schematic Systems and VHDL/Verilog

Contents of the Course (cont’d) 2 ASIC labs 2 FPGA labs Transistor/Layout Gate and Schematic Systems/VHDL (Cadence) (Xilinx Foundation) (Synopsys)

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