Computer architecture Lecture 11: Reduced Instruction Set Computers Piotr Bilski

Characteristics of the RISC architecture Processor contains large number of the general purpose registers RISC compilers use procedures for the register usage optimization Number of the instructions is small in comparison with CISC architecture Instructions have basic structure Instruction pipeline is optimized

Comparison between the selected processors Parameter IBM 370 VAX SPARC MIPS R4000 PowerPC Ultra Sparc Prod. year Instructions number Instruction size 2-6 B2-57 B1-11 B4 B Addressing modes Register number Cache size64 kB 8 kB32 kB128 kB16/32 kB32 kB

RISC and the programming languages High-level language – alleviations for the programmer, multiple hidden details Necessity to translate high-level language into the machine language Small high-level programs  large machine programs Increase of the effectiveness requires construction of the complex compilers

Characteristics of the executed instructions Instruction types – instructions executed by the processor Types and number of the instruction arguments Instruction scheduling – pipelining

Analysis of the frequency of the executed instructions [%] LanguagePascalFortranPascalCSAL TaskScientificStudentSystem Assigning Loops43534 Call If Goto29030 Other07616

Dynamic occurence Weighted according to the machine instruction Weighted according to the memory reference Language PascalC C C ASSIGN45%38%13% 14%15% LOOP5%3%42%32%33%26% CALL15%12%31%33%44%45% IF29%43%11%21%7%13% GOTO03%0000 other6%1%3%1%2%1% Analysis of the frequency of the executed instructions (cont.)

Arguments processed by the instructions PascalCAverage Constant numbers 16 %23 %20 % Scalar variables 58 %53 %55 % Tables/ structures 26 %24 %25 %

Exploitation of the arguments in the procedure calls Programs including:Compiler, interpreter Small, non-numerical programs 3-4 arguments0-7 %0-5 % 5-7 arguments0-3 %0 % 8-11 arguments1-20 %0-6 % 12 and more arguments 1-6 %0-3 %

Register tables Requirement for the assignment operations optimization – registers Local variables should be stored in one register block Problem of passing arguments to funcions and returning variables Nested function calls and the number of the registers

Register windows Functions use small number of the local variables, so every function requires small number of registers Every function has different set of the registers assigned (so-called window) Neighbor windows overlap, allowing to pass arguments between functions

Register windows - organization Parameter registers Local registers Temporary registers Parameter registers Local registers Temporary registers level I level I+1 Call/return

Window registers - example Current window pointer (CWP) Saved window pointer (SWP)

Global variables Handled by the global registers set Problem of the global register addressing in the window – uniform addressing mode Decision about assignment of the variables to the register depends on the compiler

Registers table and cache Large register tableCache memory All local scalarsRecently used local scalars Single variablesMemory blocks Global variables pointed by the compiler Global variables recently used Variables stored depending on the function nesting Variables stored depending on the swap algorithm Register addressingMemory addressing

Registers table and cache (cont.) R Instruction Decoder Row number Data A Instruction comparison Data Pointers a) b)

Register olptimization using compiler For the small number of registers, decision must be made, which variables should be assigned to them An infinite number of the symbolic registers is created, which are further mapped onto the real registers Assignment is the graph coloring problem

Graph coloring example Vertices are symbolic registers Colors are real registers Register interference

Problems of the compiler design Does smaller program mean smaller machine code? Are programs containing more complex procedures faster? proc. 1proc. 2proc. 3 RISC I1,0 VAX 110,80,67 M680000,9

RISC instruction characteristics One instruction executed during the cycle Data transfer operations „from register to register” Only simple addressing modes Simple instruction formats

RISC machine instruction One instruction during one machine cycle Machine cycle is the time required to fetch two arguments from registers, performing ALU operation and storing result into the register no microcode, instruction executed by the hardware!

Data transfer register-register All data should be in registers Exceptions are memory references (LOAD, STORE) Smaller instruction list, simpler control unit AddBCA ACB SubtractBDD AddrArBrC AddrBrArC SubtractrD rB Instruction size = 168 B Instruction size = 60 B

Simple instruction formats All instructions have constant size! Simple instructions are easier to optimize during compilation ALU for the simpler instructions is simpler and faster Pipelining is more effective Easier interrupt handling The most frequently executed instructions can be implemented in the hardware

CISC vs RISC ProcessorTypeInstruction size Indirect addressing Argument number R2000RISC4 Bno1 SPARCRISC4 Bno1 IBM RS/6000RISC4 Bno1 Intel i860RISC4 Bno CISC12 Bno2 M68040CISC22 Byes2 VAXCISC56 Byes6

Pipelining Register-to-register processing –Instruction fetching (F) –Instruction execution (E) Loading and writing into memory –Instruction fetching (F) –Instruction execution (E) –Memory operation (M)

Sequential operation and pipelining F E M

Pipelining 2-stage – one memory access 3-stage – two memory accesses 4-stage F E M F E F E M F E M F F E 1 E 2 M

Pipelining with branch Program: 100 LOAD X,A 101 ADD 1,A 102 JUMP ADD A,B 104 SUB C,B 105 STORE A,Z F E M F E F F E M

Insertion of the empty instruction Program: 100 LOAD X,A 101 ADD 1,A 102 JUMP NOOP 106 STORE A,Z F E M F E F E M F E

Reversed instruction sequence Program: 100 LOAD X,A 101 JUMP ADD 1,A 105 STORE A,Z F E M F E F E M

RISC example – MIPS R bit architecture processor (with such registers and ALU bus) In the R4000 there is one processor and one Memory Management Unit – MMU 32 general purpose registers, up to 128 kB of the cache memory (half for the instructions and data) Constant instruction format – 4 bytes No conditional codes Three instruction formats

MIPS R4000 instruction formats Operation rs rt Immediate OperationTarget Operation rs rt rd offset function Operation with the immediate operand branch Register addressing

RISC example – Sun SPARC processor uses register windows (2 to 32 windows 24 registers each) Eight global registers (0-7) Output registers (called with the called procedure, 8-15) Input registers (used with the calling procedure, 24-31) Local registers, labelled with All instructions 32-bit long

SPARC instruction formats Op relative shifting of the program counter 2 30 Op a cond. op2 rel. shift. of the progr. Count Op Target op2 Immediate constant Op Target Op3 Src-1 FP-op Src Op Target Op3 Src-1 0 dism. Src Op Target Op3 Src-1 1 Imm. constant call branch SETHI Floating point format Generic format