A 16-Bit Low-Power Microcontroller with Monolithic MEMS-LC Clocking Eric D. Marsman1, Robert M. Senger1, Michael S. McCorquodale2, Matthew R. Guthaus1, Rajiv A. Ravindran1, Ganesh S. Dasika1, Scott A. Mahlke1, Richard B. Brown3 1University of Michigan, 2Mobius Microsystems, 3University of Utah IEEE International Symposium on Circuits and Systems May 23rd – May 26th, 2005, Kobe, Japan

Overview Motivation Microsystem Architecture Microcontroller Clock Generation Dynamic Frequency Scaling (DFS) Microsystem Measured Results Compiler Utilization Instruction Level Power Modeling DFS Future Directions Conclusion

Motivation Wireless Integrated Microsystems (WIMS) Environmental Sensors Biomedical Implants Cochlear Implant Heavy Metals Deep Brain Implants m Gas Chromatograph

Commercially available cores Motivation (cont) Power minimization Frequency scaling Voltage scaling Memory architecture Process technology Leakage current mitigation Core Process Frequency No. Bits Core Power ARM7TDMI 0.18um 88MHz 32 22mW Tensilica Xtensa 200MHz 80mW MIPS32M4K 0.13um 300MHz 84mW Infineon C166S 80MHz 16 160mW Commercially available cores

Microsystem Architecture 16-bit, 3-stage pipeline Software controlled register interface to clock generator Peripheral communication interfaces for flexibility

Microcontroller Architecture Primarily a Load-Store architecture 77 instructions, 8 addressing modes Data and address registers split into two windows Hardware support for one level of interrupts and subroutines Banked memory architecture with additional external memory interface Energy/area tradeoffs compared to single 64kB bank Low-power loop cache for commonly executed instructions 15.9% more area 69.2% less power

Monolithic Clock Generation Complementary, cross coupled, negative-transconductance tank Frequency trimming via modulation of tail current with vtrim CMOS compatible 1.056GHz oscillation frequency Buffer amplifier removes amplitude variation

Dynamic Frequency Scaling Fully synthesized logic, no custom design Synchronization chain ensures glitch free output Optional external clock input

Dynamic Frequency Scaling (cont) Glitch suppression example

Microsystem Measured Results TSMC 0.18mm MM/RF bulk CMOS 3.5 million transistors Operates up to 92MHz 33.9mW core power consumption @ 92MHz & 1.8V 1.4mW core power consumption @ 10MHz & 1.1V 17.28mW MEMS clock source power consumption @ 1.8V 740mW sleep power consumption @ 1.1V 3.54mm

Microcontroller Measured Results Static loop cache utilization provides 4 to 20% energy savings Vdd scaling across different frequencies allows for adjustment to program workload requirements Loop cache energy savings Power vs. Vdd across frequency ranges

Energy savings in 64B loop cache WIMS C Compiler Windowed versus non-windowed machine 19% reduction in power consumption 30% performance improvement Dynamic instruction placement in 512B loop cache achieves 43% energy savings over static placement Energy savings in 64B loop cache

Instruction Level Power Modeling Divide ISA into groups of similar instructions noops model inter-instruction pipeline switching Account for memory access energy separately Instruction Group Energy (nJ) add-sub 0.2403 win swap 0.1832 shift 0.1950 load imm 0.1961 boolean 0.2127 branch-nt 0.1720 compare 0.2082 branch-t 0.5741 multiply 2.7702 jmp abs 0.5372 divide 2.7160 jmp rel 0.4020 copy jmp abs sub 0.5658 bit 0.6137 jmp rel sub 0.3527 load abs 0.5249 return 0.3700 load rel 0.3661 swi 0.5585 store abs 0.4427 store rel 0.3070 noop 0.1931 Ext Mem (nJ)1 Loop (nJ) MMR (nJ) Boot Rom (nJ) inst fetch -0.0554 -0.0507 - -0.0420 bit2 -0.1643 -0.1615 -0.1909 load abs2 -0.0976 -0.1016 -0.0877 load rel2 -0.1039 -0.1091 store abs2 -0.0411 -0.0461 -0.0427 store rel2 -0.0525 -0.0633 -0.0575 1 Excludes memory access energy as this is memory dependent 2 Fetch energy counted separately Memory access energy Energy per instruction group

Clock Generation Results No external reference No PLL/DLL High frequency accuracy Low start-up latency Low temperature coefficient Broad operating temperature range Low jitter Minimal area overhead (3% of die) Low Power All Si technology Metric/Parameter LC Clock Reference frequency 1056MHz Output frequencies 0.002 – 66MHz Frequency accuracy across lot ±0.75% Frequency precision (no trim) ±2% Trimmed frequency accuracy 100ppm Worst case duty cycle 48/52 Worst case RMS period jitter <300ppm Temperature stability ±0.9% (-40 to 100C) Max. operation temperature 150C Power supply 1.8V Bias current 9.6mA Power dissipation 17.28mW Min. operating power 7.2mW Start-up latency (25C/125C) 18ns/28ns Si footprint 0.3mm2

MEMS Fabrication Post processing etch using PAD cut Suspended inductor Varactor etch unsuccessful No etch chemistry for MiM oxy-nitride dielectric Use transconductance modulation instead By the way, the deal with the varactors was that we were trying to make very small-gap varactors out of the MiM structure in order to reduce microphonic sensitivity. However, the dielectric for the MiM is an oxy-nitride and though we had a chemistry for etching oxide in the presence of Al, we could not determine one for oxy-nitride in the presence of Al.

DFS Results Glitch free switching Switching latency is 5/2f0, or 37.45ns for this implementation

Preliminary next generation system Future Directions Add DSP for Cochlear Implants and other bio-medical devices Include ring oscillator for a lower power alternative ISA improvements to reduce compiler bottlenecks Address register support Separate data and address register windows DMA instructions Decrease sleep mode power Explore Microsystem design in advanced technologies 3.0mm Preliminary next generation system

Conclusion Described a highly-functional, low-power Microsystem ideally suited for remote and bio-medical applications DFS allows on-the-fly, low-latency adaptation to workload requirements from 33.9mW @ 90MHz to 1.4mW @ 10MHz or sleep mode at 740mW Monolithic clock reference decreases system size, cost, and power consumption compared to other techniques Power-aware compiler takes advantage of low-power architectural features to achieve maximum power reduction

Acknowledgements NSF ERC for WIMS MOSIS Educational Program Artisan Components TSMC Cadence Synopsys Mentor Graphics Coventor