25/05/2010 RD51 Collaboration Meeting Cisbani-Musico-Minutoli / Status JLab Electronics 1 Status of the APV25 electronics for the GEM tracker at JLab Evaristo Cisbani - INFN/Rome & Italian National Institute of Health On behalf of: Paolo Musico, Saverio Minutoli, Giuseppe Gariano - INFN/GE Bari 09/October/10 WG5-RD51 Collaboration Meeting

SBS Spectrometer in Hall A SiD Large luminosity Moderate acceptance Forward angles Reconfigurable detectors Large luminosity Moderate acceptance Forward angles Reconfigurable detectors 21 Set 2010 / CSN III JLab12 – - E. Cisbani 2 Electronics for: Small silicon detector (SiD) Front GEM tracker Large backward GEM trackers  >100k channels

Readout Foil 21 Set 2010 / CSN III JLab12 – - E. Cisbani 3 No soldering, very thin connections Laser cutting required

25/05/2010 RD51 Collaboration Meeting Cisbani-Musico-Minutoli / Status JLab Electronics 4 Electronics Components GEM  FEC  ADC+VME Controller  DAQ Main features: Use analog readout APV25 chips 2 active components: Front-End card and VME64x custom module Copper cables between front-end and VME 2D Readout Thanks to Michael Böhmer and Igor Konorov from TUM for very productive discussions on the design of the APV25 based FrontEnd card 75 mm 49.5 mm 8 mm Up to 10m twisted, shielded copper cable

25/05/2010 RD51 Collaboration Meeting Cisbani-Musico-Minutoli / Status JLab Electronics 5 Front End Card (Proto 1) GEM  FEC  ADC+VME Controller  DAQ Analog Output Panasonic FPC connectors Input Protection diodes APV25 bonding on PCB Voltage regulators Analog Driver Thermometer Digital IN Power Line I2C

25/05/2010 RD51 Collaboration Meeting Cisbani-Musico-Minutoli / Status JLab Electronics 6 Front End Card (Proto 1) GEM  FEC  ADC+VME Controller  DAQ Analog Output Input Protection diodes Panasonic FPC connectors Analog driver (not used) Voltage rogulators Thermometer 2 In/Out options APV25 bonding on PCB Digital Input + Power supply Analog out + Digital Input + Power supply APV25

VME64x Controller (Proto 0)  VME controller hosts the digitization of the analog signals coming from the front-end card.  It handle all control signals required by the front end cards (up to 16 FE)  Compliant to the new JLab/12 VME64x VITA 41 (VXS) standard  We intend to make it accessible by standard VME as well  Modular design: with the possibility to easily detach the analog module to extend FEC- VME64x distance  Version 1 submitted for production From the VXS backplane: 1.Trigger L1/L2 2.Synch 3.Clock 4.Busy (OUT) (duplicated on front panel) Digital OUT 16 Analog IN Analog Receivers ADCs 50 MHz 12 bits USB ETH Optical Fiber 2x64Mbyte SDRAM Live Insertion Hot-Swap Oscillators (100 MHz, 62.5 MHz) Flash EPROM Thermometer Voltage Regulators for each module 21 Set 2010 / CSN III JLab12 – - E. Cisbani 7

25/05/2010 RD51 Collaboration Meeting Cisbani-Musico-Minutoli / Status JLab Electronics 8 Electronic layout on one chamber Cards and modules are supported by an outer carbon-fiber frame which runs all around the chamber. Front-end cards are electromagnetically shielded by backplane and carbon-fiber (with thin conductive tape)

GEM Electronics Layout 21 Set 2010 / CSN III JLab12 – - E. Cisbani 9 1.Use high density, high quality, standard HDMI (A-type for digital signals, B-type for analogo output) 2.Analog and digital lines rus independently 3.Analog and Digital patch panels collects and reroute channels 4.Similar solution for the SiD planes

Beam DESY (EUDET support) 25/05/2010 RD51 Collaboration Meeting Cisbani-Musico-Minutoli / Status JLab Electronics 10 4 front-end cards (proto 0) on a 10x10 2xGEM With 2D readout (a la COMPASS)

Evidence of the beam 25/05/2010 RD51 Collaboration Meeting Cisbani-Musico-Minutoli / Status JLab Electronics 11 No BEAM Beam Relevant noise, partially suppressed by common noise subtractio Large pedestal fluctuation

Cable lenght study 21 Set 2010 / CSN III JLab12 – - E. Cisbani 12 Test new electronics Improve noise suppression Test cable length Test 2xGEM chamber

To do list Add PLL for fine clock-ADC convert phase tuning (already implemented in hardware in second version) Coherent event builder Use of external memory Median evaluation and common noise subtraction on FPGA Zero suppression 25/05/2010 RD51 Collaboration Meeting Cisbani-Musico-Minutoli / Status JLab Electronics 13

25/05/2010 RD51 Collaboration Meeting Cisbani-Musico-Minutoli / Status JLab Electronics 14 Conclusions Front-end card prototype 1: tested, can be considered final version VME-controller prototype 0: –Bug fixed –Most of the basic firmware implemented –New version under production Expect to install in GEM module (40x50cm2) in November – test end of November