1 COMPUTER ARCHITECTURE (for Erasmus students) Assoc.Prof. Stasys Maciulevičius Computer Dept.

©S.Maciulevičius Interrupts  Much of the functionality embedded inside a computer is implemented by hardware devices other than the processor  Since each device operates at its own pace, a method is needed for synchronizing the operation of the processor with these devices  There are two basic ways that the processor could do this:  Polling: The processor could take turns going to each device and asking if they have anything they need it to do. This is called polling the devices  Interrupting: The other way that the processor can handle information transfers is to let the devices request them when they need its attention. This is the basis for the use of interrupts

©S.Maciulevičius Polling  First, it is very wasteful in terms of processing power, since the processor is constantly busy reading the status of the attached devices instead of executing some useful code  Second, when the rate of data transfer is extremely high, the processor might lose data bytes arriving from the hardware devices

©S.Maciulevičius Interrupting  Instead of polling hardware devices to wait for their response, each device is responsible for notifying the processor about its current state  When a hardware device needs the processor's attention, it simply sends an electrical signal (hardware interrupt) through a dedicated pin in the interrupt controller chip (located on the computer's motherboard)

©S.Maciulevičius Interrupts  A message from one part of the computer to another (normally to the system processor) that tells it that it needs to stop what it is doing, and do something else instead is called interrupt  An IRQ is an interrupt request, and is the name for the actual signal that is used when a peripheral requests an interrupt of the processor  In addition to the hardware interrupts, there are also software interrupts. These are used by various software programs in response to different events that occur as the operating system and applications run

©S.Maciulevičius Interrupts Interrupting (Interrupt handling) programs Interrupt requests Main program Processor Environment

©S.Maciulevičius Interrupt types External interrupts (asynchronous to current process): hardware faults (power, …) timer other processes or processors processes in external devices user, operator Internal interrupts – exceptions (synchronous to current process): addressing errors operand errors (/0, …) operation errors (overflow, …) invalid operation mode changing

©S.Maciulevičius Interrupt types Software interrupts (synchronous to current proces s ): software interrupts (for testing) debugging interrupts Switching to interrupt handling : after completing of inctruction (most often) during execution of inctruction (rarely) when execution fails (e.g., page fault) Interrupt handling: at microprogram level (rarely) at program level (most often)

©S.Maciulevičius How often are interrupts? Analysis of interrupts in VAX 8800 computer, working in multitasking mode, has shown: Interrupt reasonInterval Input/output system2,7 ms System timer10,0 ms Software interrupts1,5 ms Hardware interrupts2,1 ms Estimating all reasons 0,9 ms

©S.Maciulevičius Interrupts Parameters: number of request lines response time switching time nesting Main progr. IRQ Interrupt handling Response Switching time (latency) time

©S.Maciulevičius Interrupt levels Requests Single level system Multi level system Interrupt priority levels Interrupt handling order:

©S.Maciulevičius Interrupt handling Interrupt handling procedure: reception of an interrupt signal interrupt identification saving current program state exexuting of interrupting (interrupt handling) program restoring saved program state

©S.Maciulevičius Interrupt handling  When a device asserts its interrupt request signal, it must be processed in an orderly fashion  All CPUs, and many devices, have some mechanism for enabling/disabling interrupt recognition and processing:  At the device level, there is usually an interrupt control register with bits to enable or disable the interrupts that device can generate  At the CPU level, a global mechanism functions to inhibit/enable (often called the global interrupt enable) recognition of interrupts

©S.Maciulevičius Interrupt handling  Systems with multiple interrupt inputs provide the ability to mask (inhibit) interrupt requests individually and/or on a priority basis. This capability may be built into the CPU or provided by an external interrupt controller. Typically, there are one or more interrupt mask registers, with individual bits allowing or inhibiting individual interrupt sources  There is often also one non-maskable interrupt input to the CPU that is used to signal important conditions such as pending power fail, reset button pressed

©S.Maciulevičius Interrupt handling in IBM/360 Int.request (2 class) New PSW Interrupting program Old PSW Interrupted program Status storing Program Status restoring PSW register

©S.Maciulevičius Interrupt controller  The interrupt controller serves as an intermediate between the hardware devices and the processor  Its responsibility is to alert the processor when one of the hardware devices needs its immediate attention  In this case, the processor stops its current activity and jumps to execute a function (interrupt handler) which was previously associated with the calling device (or more accurately, associated with the interrupt vector of the device)

©S.Maciulevičius Interrupt controller (Intel)  The Intel 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU  It is cascadable for up to 64 vectored priority interrupts without additional circuitry  The 8259A is designed to minimize the software and real time overhead in handling multi-level priority interrupts.

©S.Maciulevičius Interrupt controller (Intel) INTA INT D 7 - D 0 IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 Control logic Interrupt request register (IRR ) Prioritety resolver Interrupt service register (ISR) Interrupt mask register (IMR) Data bus buffer Read/ Write logic Kaskadinio jungimo valdymas RD WR A 0 CS CAS 0 CAS 1 CAS 2 SP/EN

©S.Maciulevičius Interrupt controller IOWC IORC INTA IRQ lines Data bus Address selector Address bus To CPU For cascading CS A 0 INT D 7 -D 0 WR RD 8259A CAS INTA IR0 IR7

©S.Maciulevičius Interrupt controllers in PC/AT IR0 IR1 INT IR2 … IR7 CAS Perif.device 02 Perif.device 03 Perif.device 09 Perif.device 10 Perif.device 11 Perif.device 15 IR0 IR1 INT IR2 IR3 IR4 IR5 IR6 IR7 CAS NMI INTR Master 8259A Slave 8259A Processor Perif.device 00 Perif.device 01  PC/XT computers have only one chip 8259A  PC/AT computers have two chips 8259A, cascadded as follows:

©S.Maciulevičius Interrupt vector  An interrupt vector is the memory address of an interrupt handler, or an index into an array called an interrupt vector table  Interrupt vector tables contain the memory addresses of interrupt handlers. When an interrupt is generated, the processor saves its execution state via a context switch, and begins execution of the interrupt handler at the interrupt vector OS Vectors occupied by the master 8259A Vectors occupied by the slave 8259A DOS8h - Fh70h - 77h Windows 95 / 9850h - 57h58h - 5Fh Windows NT30h - 37h38h - 3Fh

©S.Maciulevičius Exceptions  Exceptions belong to a special type of software interrupts  They are generated by the processor itself whenever some unexpected critical event occurs  For instance, a page fault exception (interrupt 14) is triggered when the processor attempts to access a page, which is marked as not-present. The exception handler can then reload the page from disk (virtual memory) and restart the instruction which generated the exception

©S.Maciulevičius Exceptions  Three types of exceptions can be generated by the processor: faults, traps and aborts  When a fault exception occurs, the CS and (E)IP registers which are pushed on the stack, point to the address of the instruction, which generated the exception. This gives the exception handler a chance to fix the condition which caused the exception to occur, before restarting the faulting instruction  Traps are similar to interrupts in the sense that they make the processor push the address of the next instruction to the stack  Aborts neglect to specify the location of the faulting instruction, since they are usually used to indicate severe errors (such as hardware errors or illegal system tables) which are not recoverable

©S.Maciulevičius Some exceptions (in real-mode) ExceptionVectorCondition Division by Zero 0 Attempting to execute a DIV or an IDIV instruction with a divisor which equals zero. Debug / Single Step 1 Used in conjunction with the debug registers to indicate a breakpoint hit. The processor also issues this interrupt after executing every instruction when the TRAP flag is set Overflow4 When performing arithmetic instructions with signed operands, the processor set the OF flag to indicate an overflow. The INTO instruction tests this flag and if it is set - generates an exception Invalid Opcode 6 Occurs when the processor executes one of the reserved opcodes or uses the LOCK prefix improperly. Can also indicate an invalid operand following an opcode